ENGR00173645 [MX6]Implement low power actions into DSM

1. Need to follow right programming model for wb_per_at_lpm
   ,zeroed wb_count each time exit from DSM and set it before
   entering DSM;
2. For TO1.1, need to set fet_odrive for better power gate.

Signed-off-by: Anson Huang <b20788@freescale.com>

diff --git a/arch/arm/mach-mx6/crm_regs.h b/arch/arm/mach-mx6/crm_regs.h
index 354d28b3f2e77aa6af75c9aca1ce62edd8c6163f..0e29ea83f1df894c61dccab54c3f81a0c6525f53 100644 (file)
--- a/arch/arm/mach-mx6/crm_regs.h
+++ b/arch/arm/mach-mx6/crm_regs.h
@@ -185,8 +185,8 @@
 #define MXC_CCM_CCR_RBC_EN                     (1 << 27)
 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK                (0x3F << 21)
 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET      (21)
-#define MXC_CCM_CCR_WB_COUNT_MASK              (0x7)
-#define MXC_CCM_CCR_WB_COUNT_OFFSET            (1 << 16)
+#define MXC_CCM_CCR_WB_COUNT_MASK              (0x7 << 16)
+#define MXC_CCM_CCR_WB_COUNT_OFFSET            (16)
 #define MXC_CCM_CCR_COSC_EN                    (1 << 12)
 #define MXC_CCM_CCR_OSCNT_MASK                 (0xFF)
 #define MXC_CCM_CCR_OSCNT_OFFSET               (0)

diff --git a/arch/arm/mach-mx6/pm.c b/arch/arm/mach-mx6/pm.c
index 381cc1d7a573474a9cbdaf90c51a1597225565d9..4771193c54783744b28ac670b410f9e2f6a80f6b 100644 (file)
--- a/arch/arm/mach-mx6/pm.c
+++ b/arch/arm/mach-mx6/pm.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *  Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -164,7 +164,8 @@ static void mx6_suspend_restore(void)
        /* Per spec, the count needs to be zeroed and reconfigured on exit from
         * low power mode
         */
-       __raw_writel(ccm_ccr & ~MXC_CCM_CCR_REG_BYPASS_CNT_MASK, MXC_CCM_CCR);
+       __raw_writel(ccm_ccr & ~MXC_CCM_CCR_REG_BYPASS_CNT_MASK &
+               ~MXC_CCM_CCR_WB_COUNT_MASK, MXC_CCM_CCR);
        udelay(50);
        __raw_writel(ccm_ccr, MXC_CCM_CCR);
        __raw_writel(ccm_clpcr, MXC_CCM_CLPCR);

diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c
index fae41383eaab8eef5a0afe0d2c924306edf70314..efc838e0807804964e22dc010ac95158e0d35eb6 100644 (file)
--- a/arch/arm/mach-mx6/system.c
+++ b/arch/arm/mach-mx6/system.c
@@ -18,6 +18,7 @@
 
 #include <linux/kernel.h>
 #include <linux/clk.h>
+#include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/regulator/consumer.h>
 #include <linux/pmic_external.h>
@@ -27,6 +28,7 @@
 #include <asm/proc-fns.h>
 #include <asm/system.h>
 #include "crm_regs.h"
+#include "regs-anadig.h"
 
 #define SCU_CTRL                                       0x00
 #define SCU_CONFIG                                     0x04
@@ -38,18 +40,13 @@
 #define GPC_PGC_CPU_PDN_OFFSET         0x2a0
 #define GPC_PGC_CPU_PUPSCR_OFFSET      0x2a4
 #define GPC_PGC_CPU_PDNSCR_OFFSET      0x2a8
-#define ANATOP_REG_2P5_OFFSET          0x130
-#define ANATOP_REG_CORE_OFFSET         0x140
 
 #define MODULE_CLKGATE         (1 << 30)
 #define MODULE_SFTRST          (1 << 31)
-static DEFINE_SPINLOCK(wfi_lock);
 
 extern unsigned int gpc_wake_irq[4];
 extern int mx6q_revision(void);
 
-static unsigned int cpu_idle_mask;
-
 static void __iomem *gpc_base = IO_ADDRESS(GPC_BASE_ADDR);
 
 extern void (*mx6_wait_in_iram)(void);
@@ -129,10 +126,27 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
                        __raw_writel(0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET);
                        __raw_writel(0x1, gpc_base + GPC_CNTR_OFFSET);
                        /* Enable weak 2P5 linear regulator */
-                       anatop_val = __raw_readl(anatop_base + ANATOP_REG_2P5_OFFSET);
-                       anatop_val |= 1 << 18;
-                       __raw_writel(anatop_val, anatop_base + ANATOP_REG_2P5_OFFSET);
-                       __raw_writel(__raw_readl(MXC_CCM_CCR) | MXC_CCM_CCR_RBC_EN, MXC_CCM_CCR);
+                       anatop_val = __raw_readl(anatop_base +
+                               HW_ANADIG_REG_2P5);
+                       anatop_val |= BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG;
+                       __raw_writel(anatop_val, anatop_base +
+                               HW_ANADIG_REG_2P5);
+                       if (mx6q_revision() != IMX_CHIP_REVISION_1_0) {
+                               /* Enable fet_odrive */
+                               anatop_val = __raw_readl(anatop_base +
+                                       HW_ANADIG_REG_CORE);
+                               anatop_val |= BM_ANADIG_REG_CORE_FET_ODRIVE;
+                               __raw_writel(anatop_val, anatop_base +
+                                       HW_ANADIG_REG_CORE);
+                       }
+                       __raw_writel(__raw_readl(MXC_CCM_CCR) |
+                               MXC_CCM_CCR_RBC_EN, MXC_CCM_CCR);
+                       /* Make sure we clear WB_COUNT and re-config it */
+                       __raw_writel(__raw_readl(MXC_CCM_CCR) &
+                               (~MXC_CCM_CCR_WB_COUNT_MASK), MXC_CCM_CCR);
+                       udelay(50);
+                       __raw_writel(__raw_readl(MXC_CCM_CCR) | (0x1 <<
+                               MXC_CCM_CCR_WB_COUNT_OFFSET), MXC_CCM_CCR);
                        ccm_clpcr |= MXC_CCM_CLPCR_WB_PER_AT_LPM;
                }
        }