The shared "Reset" registers are sequential in the enum ni_gpct_register.
Replace this inline CamelCase function with a simple define.
Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter)
{
write_register(counter, Gi_Reset_Bit(counter->counter_index),
- NITIO_Gxx_Joint_Reset_Reg(counter->counter_index));
+ NITIO_RESET_REG(counter->counter_index));
}
void ni_tio_init_counter(struct ni_gpct *counter)
#define NITIO_CNT_MODE_REG(x) (NITIO_G0_CNT_MODE + (x))
#define NITIO_GATE2_REG(x) (NITIO_G0_GATE2 + (x))
#define NITIO_STATUS_REG(x) (NITIO_G01_STATUS + ((x) / 2))
-
-static inline enum ni_gpct_register NITIO_Gxx_Joint_Reset_Reg(unsigned idx)
-{
- switch (idx) {
- case 0:
- case 1:
- return NITIO_G01_RESET;
- case 2:
- case 3:
- return NITIO_G23_RESET;
- }
- return 0;
-}
+#define NITIO_RESET_REG(x) (NITIO_G01_RESET + ((x) / 2))
static inline enum ni_gpct_register NITIO_Gxx_Joint_Status1_Reg(unsigned idx)
{