ASoC: Fix WM8996 24.576MHz clock operation

commit 37d5993c5cc9bc83762ae1b5bd287438022e8afe upstream.

Record the clock after the divider as that is what all SYSCLK users see.
Without this the other clock configuration in the device comes out at
half rate.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

diff --git a/sound/soc/codecs/wm8996.c b/sound/soc/codecs/wm8996.c
index c9c4e5c5949455d44aa3b437c3eb70dc59505cfa..5c40874811e074be9ae58fca57a94df7123397b8 100644 (file)
--- a/sound/soc/codecs/wm8996.c
+++ b/sound/soc/codecs/wm8996.c
@@ -1895,6 +1895,7 @@ static int wm8996_set_sysclk(struct snd_soc_dai *dai,
                break;
        case 24576000:
                ratediv = WM8996_SYSCLK_DIV;
+               wm8996->sysclk /= 2;
        case 12288000:
                snd_soc_update_bits(codec, WM8996_AIF_RATE,
                                    WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);