ENGR00153127 ENET: Enet not works in 1G mode

Mx6 not works when connnect to a 1G switch.
This is caused by phy_dev->supported != PHY_GBIT_FEATURES, more bits
will set to phy_dev->supported when negotiation complete.

Signed-off-by: Zeng Zhaoming <b32542@freescale.com>

diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index eaf9420844e4050aa91151bb869170e390c8e977..79eba696589643dc913fc1b631c364cecf2f1b2b 100644 (file)
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -337,150 +337,6 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
        return NETDEV_TX_OK;
 }
 
-/* This function is called to start or restart the FEC during a link
- * change.  This only happens when switching between half and full
- * duplex.
- */
-static void
-fec_restart(struct net_device *ndev, int duplex)
-{
-       struct fec_enet_private *fep = netdev_priv(ndev);
-       const struct platform_device_id *id_entry =
-                               platform_get_device_id(fep->pdev);
-       int i;
-       u32 temp_mac[2];
-       u32 rcntl = OPT_FRAME_SIZE | 0x04;
-
-       /* Whack a reset.  We should wait for this. */
-       writel(1, fep->hwp + FEC_ECNTRL);
-       udelay(10);
-
-       /*
-        * enet-mac reset will reset mac address registers too,
-        * so need to reconfigure it.
-        */
-       if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
-               memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
-               writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
-               writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
-       }
-
-       /* Clear any outstanding interrupt. */
-       writel(0xffc00000, fep->hwp + FEC_IEVENT);
-
-       /* Reset all multicast. */
-       writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
-       writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
-#ifndef CONFIG_M5272
-       writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
-       writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
-#endif
-
-       /* Set maximum receive buffer size. */
-       writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
-
-       /* Set receive and transmit descriptor base. */
-       writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
-       writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
-                       fep->hwp + FEC_X_DES_START);
-
-       fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
-       fep->cur_rx = fep->rx_bd_base;
-
-       /* Reset SKB transmit buffers. */
-       fep->skb_cur = fep->skb_dirty = 0;
-       for (i = 0; i <= TX_RING_MOD_MASK; i++) {
-               if (fep->tx_skbuff[i]) {
-                       dev_kfree_skb_any(fep->tx_skbuff[i]);
-                       fep->tx_skbuff[i] = NULL;
-               }
-       }
-
-       /* Enable MII mode */
-       if (duplex) {
-               /* FD enable */
-               writel(0x04, fep->hwp + FEC_X_CNTRL);
-       } else {
-               /* No Rcv on Xmit */
-               rcntl |= 0x02;
-               writel(0x0, fep->hwp + FEC_X_CNTRL);
-       }
-
-       fep->full_duplex = duplex;
-
-       /* Set MII speed */
-       writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
-
-       /*
-        * The phy interface and speed need to get configured
-        * differently on enet-mac.
-        */
-       if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
-               /* Enable flow control and length check */
-               rcntl |= 0x40000000 | 0x00000020;
-
-               /* MII or RMII */
-               if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
-                       rcntl |= (1 << 8);
-               else
-                       rcntl &= ~(1 << 8);
-
-               /* 10M or 100M */
-               if (fep->phy_dev && fep->phy_dev->speed == SPEED_100)
-                       rcntl &= ~(1 << 9);
-               else
-                       rcntl |= (1 << 9);
-
-       } else {
-#ifdef FEC_MIIGSK_ENR
-               if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
-                       /* disable the gasket and wait */
-                       writel(0, fep->hwp + FEC_MIIGSK_ENR);
-                       while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
-                               udelay(1);
-
-                       /*
-                        * configure the gasket:
-                        *   RMII, 50 MHz, no loopback, no echo
-                        */
-                       writel(1, fep->hwp + FEC_MIIGSK_CFGR);
-
-                       /* re-enable the gasket */
-                       writel(2, fep->hwp + FEC_MIIGSK_ENR);
-               }
-#endif
-       }
-       writel(rcntl, fep->hwp + FEC_R_CNTRL);
-
-       /* And last, enable the transmit and receive processing */
-       writel(2, fep->hwp + FEC_ECNTRL);
-       writel(0, fep->hwp + FEC_R_DES_ACTIVE);
-
-       /* Enable interrupts we wish to service */
-       writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
-}
-
-static void
-fec_stop(struct net_device *ndev)
-{
-       struct fec_enet_private *fep = netdev_priv(ndev);
-
-       /* We cannot expect a graceful transmit stop without link !!! */
-       if (fep->link) {
-               writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
-               udelay(10);
-               if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
-                       printk("fec_stop : Graceful transmit stop did not complete !\n");
-       }
-
-       /* Whack a reset.  We should wait for this. */
-       writel(1, fep->hwp + FEC_ECNTRL);
-       udelay(10);
-       writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
-       writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
-}
-
-
 static void
 fec_timeout(struct net_device *ndev)
 {
@@ -1403,6 +1259,170 @@ static int fec_enet_init(struct net_device *ndev)
        return 0;
 }
 
+/* This function is called to start or restart the FEC during a link
+ * change.  This only happens when switching between half and full
+ * duplex.
+ */
+static void
+fec_restart(struct net_device *dev, int duplex)
+{
+       struct fec_enet_private *fep = netdev_priv(dev);
+       const struct platform_device_id *id_entry =
+                               platform_get_device_id(fep->pdev);
+       int i;
+       u32 val, temp_mac[2];
+
+       /* Whack a reset.  We should wait for this. */
+       writel(1, fep->hwp + FEC_ECNTRL);
+       udelay(10);
+
+       /*
+        * enet-mac reset will reset mac address registers too,
+        * so need to reconfigure it.
+        */
+       if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
+               memcpy(&temp_mac, dev->dev_addr, ETH_ALEN);
+               writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
+               writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
+       }
+
+       /* Clear any outstanding interrupt. */
+       writel(0xffc00000, fep->hwp + FEC_IEVENT);
+
+       /* Reset all multicast. */
+       writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
+       writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
+#ifndef CONFIG_M5272
+       writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
+       writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
+#endif
+
+       /* Set maximum receive buffer size. */
+       writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
+
+       /* Set receive and transmit descriptor base. */
+       writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
+       writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
+                       fep->hwp + FEC_X_DES_START);
+
+       fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
+       fep->cur_rx = fep->rx_bd_base;
+
+       /* Reset SKB transmit buffers. */
+       fep->skb_cur = fep->skb_dirty = 0;
+       for (i = 0; i <= TX_RING_MOD_MASK; i++) {
+               if (fep->tx_skbuff[i]) {
+                       dev_kfree_skb_any(fep->tx_skbuff[i]);
+                       fep->tx_skbuff[i] = NULL;
+               }
+       }
+
+       /* Enable MII mode */
+       if (duplex) {
+               /* MII enable / FD enable */
+               writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
+               writel(0x04, fep->hwp + FEC_X_CNTRL);
+       } else {
+               /* MII enable / No Rcv on Xmit */
+               writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL);
+               writel(0x0, fep->hwp + FEC_X_CNTRL);
+       }
+       fep->full_duplex = duplex;
+
+       /* Set MII speed */
+       writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
+
+       /*
+        * The phy interface and speed need to get configured
+        * differently on enet-mac.
+        */
+       if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
+               val = readl(fep->hwp + FEC_R_CNTRL);
+
+               /* MII or RMII */
+               if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
+                       val |= (1 << 6);
+               else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
+                       val |= (1 << 8);
+               else
+                       val &= ~(1 << 8);
+
+               /* 10M or 100M */
+               if (fep->phy_dev && fep->phy_dev->speed == SPEED_100)
+                       val &= ~(1 << 9);
+               else
+                       val |= (1 << 9);
+
+               writel(val, fep->hwp + FEC_R_CNTRL);
+       } else {
+#ifdef FEC_MIIGSK_ENR
+               if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
+                       /* disable the gasket and wait */
+                       writel(0, fep->hwp + FEC_MIIGSK_ENR);
+                       while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
+                               udelay(1);
+
+                       /*
+                        * configure the gasket:
+                        *   RMII, 50 MHz, no loopback, no echo
+                        */
+                       writel(1, fep->hwp + FEC_MIIGSK_CFGR);
+
+                       /* re-enable the gasket */
+                       writel(2, fep->hwp + FEC_MIIGSK_ENR);
+               }
+#endif
+       }
+
+       /* ENET enable */
+       val = (0x1 << 1);
+
+       /* if phy work at 1G mode, set ENET RGMII speed to 1G */
+       if (fep->phy_dev && (fep->phy_dev->supported &
+               (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)) &&
+               fep->phy_interface == PHY_INTERFACE_MODE_RGMII &&
+               fep->phy_dev->speed == SPEED_1000)
+               val |= (0x1 << 5);
+
+       if (cpu_is_mx6q()) {
+               /* enable endian swap */
+               val |= (0x1 << 8);
+               /* enable ENET store and forward mode */
+               writel(0x1 << 8, fep->hwp + FEC_X_WMRK);
+       }
+       writel(val, fep->hwp + FEC_ECNTRL);
+
+       writel(0, fep->hwp + FEC_R_DES_ACTIVE);
+
+       /* Enable interrupts we wish to service */
+       writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
+}
+
+static void
+fec_stop(struct net_device *dev)
+{
+       struct fec_enet_private *fep = netdev_priv(dev);
+
+       /* We cannot expect a graceful transmit stop without link !!! */
+       if (fep->link) {
+               writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
+               udelay(10);
+               if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
+                       printk("fec_stop : Graceful transmit stop did not complete !\n");
+       }
+
+       /* Whack a reset.  We should wait for this. */
+       writel(1, fep->hwp + FEC_ECNTRL);
+       udelay(10);
+
+       if (cpu_is_mx6q())
+               /* FIXME: we have to enable enet to keep mii interrupt works. */
+               writel(2, fep->hwp + FEC_ECNTRL);
+
+       writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
+       writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
+}
+
 static int __devinit
 fec_probe(struct platform_device *pdev)
 {