if (spicfg->timer_disable)
spifmt |= SPIFMT_DISTIMER_MASK;
+ else
+ iowrite32((spicfg->c2tdelay << SPI_C2TDELAY_SHIFT) |
+ (spicfg->t2cdelay << SPI_T2CDELAY_SHIFT),
+ davinci_spi->base + SPIDELAY);
if (spi->mode & SPI_READY)
spifmt |= SPIFMT_WAITENA_MASK;
u32 tx_data, data1_reg_val;
u32 buf_val, flg_val;
struct davinci_spi_platform_data *pdata;
- struct davinci_spi_config *spicfg;
davinci_spi = spi_master_get_devdata(spi->master);
pdata = davinci_spi->pdata;
- spicfg = (struct davinci_spi_config *)spi->controller_data;
- if (!spicfg)
- spicfg = &davinci_spi_default_cfg;
davinci_spi->tx = t->tx_buf;
davinci_spi->rx = t->rx_buf;
/* Enable SPI */
set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
- iowrite32((spicfg->c2tdelay << SPI_C2TDELAY_SHIFT) |
- (spicfg->t2cdelay << SPI_T2CDELAY_SHIFT),
- davinci_spi->base + SPIDELAY);
-
count = davinci_spi->count;
/* Determine the command to execute READ or WRITE */
struct davinci_spi_dma *davinci_spi_dma;
int word_len, data_type, ret;
unsigned long tx_reg, rx_reg;
- struct davinci_spi_config *spicfg;
struct device *sdev;
davinci_spi = spi_master_get_devdata(spi->master);
sdev = davinci_spi->bitbang.master->dev.parent;
- spicfg = (struct davinci_spi_config *)spi->controller_data;
- if (!spicfg)
- spicfg = &davinci_spi_default_cfg;
davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
if (ret)
return ret;
- /* Put delay val if required */
- iowrite32((spicfg->c2tdelay << SPI_C2TDELAY_SHIFT) |
- (spicfg->t2cdelay << SPI_T2CDELAY_SHIFT),
- davinci_spi->base + SPIDELAY);
-
count = davinci_spi->count; /* the number of elements */
/* disable all interrupts for dma transfers */