clk: tegra: pll: Add code to handle if resets are supported by PLL

If a PLL has a reset_reg specified, properly handle that in the
enable/disable logic paths.

Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index fb3e3f67586c1de44ac314c0319b408dc2c1065a..c645a899deba5a5787f03be62ace94386a0f2b6b 100644 (file)
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -311,6 +311,12 @@ static void _clk_pll_enable(struct clk_hw *hw)
                udelay(2);
        }
 
+       if (pll->params->reset_reg) {
+               val = pll_readl(pll->params->reset_reg, pll);
+               val &= ~BIT(pll->params->reset_bit_idx);
+               pll_writel(val, pll->params->reset_reg, pll);
+       }
+
        clk_pll_enable_lock(pll);
 
        val = pll_readl_base(pll);
@@ -343,6 +349,12 @@ static void _clk_pll_disable(struct clk_hw *hw)
                writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
        }
 
+       if (pll->params->reset_reg) {
+               val = pll_readl(pll->params->reset_reg, pll);
+               val |= BIT(pll->params->reset_bit_idx);
+               pll_writel(val, pll->params->reset_reg, pll);
+       }
+
        if (pll->params->iddq_reg) {
                val = pll_readl(pll->params->iddq_reg, pll);
                val |= BIT(pll->params->iddq_bit_idx);

diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index ae09a3139df2fdcc9753a2ad95be55f043758a4e..adf2e8ead335706c226cfd933eeda0c958593ca7 100644 (file)
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -176,6 +176,8 @@ struct div_nmp {
  * @lock_enable_bit_idx:       Bit index to enable PLL lock
  * @iddq_reg:                  PLL IDDQ register offset
  * @iddq_bit_idx:              Bit index to enable PLL IDDQ
+ * @reset_reg:                 Register offset of where RESET bit is
+ * @reset_bit_idx:             Shift of reset bit in reset_reg
  * @sdm_din_reg:               Register offset where SDM settings are
  * @sdm_din_mask:              Mask of SDM divider bits
  * @sdm_ctrl_reg:              Register offset where SDM enable is
@@ -239,6 +241,8 @@ struct tegra_clk_pll_params {
        u32             lock_enable_bit_idx;
        u32             iddq_reg;
        u32             iddq_bit_idx;
+       u32             reset_reg;
+       u32             reset_bit_idx;
        u32             sdm_din_reg;
        u32             sdm_din_mask;
        u32             sdm_ctrl_reg;