ARM: dts: imx6qdl-sabrelite: fix ENET group

GPIO16 is used for I2C3, not ENET_REF_CLK.
Also, remove pull-ups from tx pins, and ENET_MDIO
which has an external pull-up.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index d443eb77eae0124727a0da50363458d481414649..0e7d314419e0711480d95064e9b82660f824d115 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -169,22 +169,21 @@
 
                pinctrl_enet: enetgrp {
                        fsl,pins = <
-                               MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
-                               MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
-                               MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
-                               MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
-                               MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
-                               MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
-                               MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
-                               MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
-                               MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                               MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b0
+                               MX6QDL_PAD_ENET_MDC__ENET_MDC           0x100b0
+                               MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x100b0
+                               MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x100b0
+                               MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x100b0
+                               MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x100b0
+                               MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x100b0
+                               MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x100b0
+                               MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
-                               MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
                                /* Phy reset */
                                MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x000b0
                        >;