mfd: Set asic3 DS1WM clock_rate

The mfd/asic3 driver does not set the ds1wm_driver_data clock_rate field
before passing the structure to the DS1WM w1 busmaster driver.
This was not noticed before commit 26a6afb, because ds1wm_find_divisor()
unintentionally returned the correct divisor when a zero clock_rate was
passed in. However after that commit DS1WM fails a zero clock_rate:

ds1wm ds1wm: no suitable divisor for 0Hz clock

This patch sets the ds1wm_driver_data clock_rate field.

Signed-off-by: Paul Parsons <lost.distance@yahoo.com>
Acked-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>

diff --git a/drivers/mfd/asic3.c b/drivers/mfd/asic3.c
index 0c083e72006a3eb9ab5952c6b7eec37db3fe5685..4bf02a8aaf360fb78597b41c78a91cb29f5ab43d 100644 (file)
--- a/drivers/mfd/asic3.c
+++ b/drivers/mfd/asic3.c
@@ -892,10 +892,13 @@ static int __init asic3_mfd_probe(struct platform_device *pdev,
        asic3_mmc_resources[0].start >>= asic->bus_shift;
        asic3_mmc_resources[0].end   >>= asic->bus_shift;
 
-       ret = mfd_add_devices(&pdev->dev, pdev->id,
+       if (pdata->clock_rate) {
+               ds1wm_pdata.clock_rate = pdata->clock_rate;
+               ret = mfd_add_devices(&pdev->dev, pdev->id,
                        &asic3_cell_ds1wm, 1, mem, asic->irq_base);
-       if (ret < 0)
-               goto out;
+               if (ret < 0)
+                       goto out;
+       }
 
        if (mem_sdio && (irq >= 0)) {
                ret = mfd_add_devices(&pdev->dev, pdev->id,

diff --git a/include/linux/mfd/asic3.h b/include/linux/mfd/asic3.h
index ed793b77a1c5e2a77301964fc8822f18c4239e1c..3fda7e589ccdcdfb8beef6fcf755599292c654e9 100644 (file)
--- a/include/linux/mfd/asic3.h
+++ b/include/linux/mfd/asic3.h
@@ -31,6 +31,8 @@ struct asic3_platform_data {
 
        unsigned int gpio_base;
 
+       unsigned int clock_rate;
+
        struct asic3_led *leds;
 };