sh: Remove implicit sign extension from assembler immediates

The SH instruction set has several instructions which accept an 8 bit
immediate operand. For logical instructions this operand is zero extended,
for arithmetic instructions the operand is sign extended. After adding an
option to the assembler to check this, it was found that several pieces
of assembly code were assuming this behaviour, and in one case
getting it wrong.

So this patch explicitly sign extends any immediate operands, which makes
it obvious what is happening, and fixes the one case which got it wrong.

Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

diff --git a/arch/sh/boot/compressed/head_32.S b/arch/sh/boot/compressed/head_32.S
index 06ac31f3be88647af51a3f1011a145b57b6ce2a5..02a30935f0b90b61fecf22da0733a046d985d806 100644 (file)
--- a/arch/sh/boot/compressed/head_32.S
+++ b/arch/sh/boot/compressed/head_32.S
@@ -22,7 +22,7 @@ startup:
        bt      clear_bss
        sub     r0, r2
        mov.l   bss_start_addr, r0
-       mov     #0xe0, r1
+       mov     #0xffffffe0, r1
        and     r1, r0                  ! align cache line
        mov.l   text_start_addr, r3
        mov     r0, r1

diff --git a/arch/sh/include/asm/entry-macros.S b/arch/sh/include/asm/entry-macros.S
index 64fd0de24dafe244ac6b9dc3e94ffbe9e8795ae8..cc43a55e1fcf4e21b102659193df16e786194e03 100644 (file)
--- a/arch/sh/include/asm/entry-macros.S
+++ b/arch/sh/include/asm/entry-macros.S
@@ -7,7 +7,7 @@
        .endm
 
        .macro  sti
-       mov     #0xf0, r11
+       mov     #0xfffffff0, r11
        extu.b  r11, r11
        not     r11, r11
        stc     sr, r10

diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S
index 8c19e21847d7f655329fef95555e633977db73af..9421ec715fd2bae428bd8254327b48023782d456 100644 (file)
--- a/arch/sh/kernel/cpu/sh3/entry.S
+++ b/arch/sh/kernel/cpu/sh3/entry.S
@@ -257,7 +257,7 @@ restore_all:
        !
        ! Calculate new SR value
        mov     k3, k2                  ! original SR value
-       mov     #0xf0, k1
+       mov     #0xfffffff0, k1
        extu.b  k1, k1
        not     k1, k1
        and     k1, k2                  ! Mask original SR value

diff --git a/arch/sh/kernel/entry-common.S b/arch/sh/kernel/entry-common.S
index 700477601c6ff787de0605e1065757eb31844027..68d9223b145eadf7ae77f5b3f332fd0b859ade0f 100644 (file)
--- a/arch/sh/kernel/entry-common.S
+++ b/arch/sh/kernel/entry-common.S
@@ -98,8 +98,9 @@ need_resched:
 
        mov     #OFF_SR, r0
        mov.l   @(r0,r15), r0           ! get status register
-       and     #0xf0, r0               ! interrupts off (exception path)?
-       cmp/eq  #0xf0, r0
+       shlr    r0
+       and     #(0xf0>>1), r0          ! interrupts off (exception path)?
+       cmp/eq  #(0xf0>>1), r0
        bt      noresched
        mov.l   3f, r0
        jsr     @r0                     ! call preempt_schedule_irq

diff --git a/arch/sh/lib/clear_page.S b/arch/sh/lib/clear_page.S
index 8342bfbde64c23a1f1128785b1ed810ba4f46b86..c92244d4ff9d74ec546ecc04d2fb6eff79b886af 100644 (file)
--- a/arch/sh/lib/clear_page.S
+++ b/arch/sh/lib/clear_page.S
@@ -57,7 +57,7 @@ ENTRY(clear_page)
 ENTRY(__clear_user)
        !
        mov     #0, r0
-       mov     #0xe0, r1       ! 0xffffffe0
+       mov     #0xffffffe0, r1
        !
        ! r4..(r4+31)&~32          -------- not aligned [ Area 0 ]
        ! (r4+31)&~32..(r4+r5)&~32 -------- aligned     [ Area 1 ]