};
&ldb {
- clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+ compatible = "fsl,imx6dl-ldb", "fsl,imx53-ldb";
+
+ clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
- clock-names = "di0_pll", "di1_pll",
+ <&clks IMX6QDL_CLK_IPU2_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>,
+ <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>,
+ <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>;
+ clock-names = "ldb_di0", "ldb_di1",
"di0_sel", "di1_sel",
- "di0", "di1";
-
- lvds-channel@0 {
- crtcs = <&ipu1 0>, <&ipu1 1>;
- };
-
- lvds-channel@1 {
- crtcs = <&ipu1 0>, <&ipu1 1>;
- };
+ "di2_sel",
+ "ldb_di0_div_3_5", "ldb_di1_div_3_5",
+ "ldb_di0_div_7", "ldb_di1_div_7",
+ "ldb_di0_div_sel", "ldb_di1_div_sel";
};