ARM: AM33XX: Add aes0 crypto clock data

Add clock data for for the SHA0 crypto module
on the am33xx SoC.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index ef0267ca2417826494f9e94b3386f96666be7e80..c8dcc523c31af6c3e7a77c96cd8fb286b5a80305 100644 (file)
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -417,6 +417,10 @@ static struct clk sha0_fck;
 DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
 DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
 
+static struct clk aes0_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
+DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
+
 /*
  * Modules clock nodes
  *
@@ -883,6 +887,7 @@ static struct omap_clk am33xx_clks[] = {
        CLK(NULL,       "smartreflex0_fck",     &smartreflex0_fck),
        CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck),
        CLK(NULL,       "sha0_fck",             &sha0_fck),
+       CLK(NULL,       "aes0_fck",             &aes0_fck),
        CLK(NULL,       "timer1_fck",           &timer1_fck),
        CLK(NULL,       "timer2_fck",           &timer2_fck),
        CLK(NULL,       "timer3_fck",           &timer3_fck),