ENGR00174232 [mx6q perfmon]PDM No. TKT055916: remove workaround for TO1.1

remove the workaround
For TO1.0: bit16 of GPR11 must be set to enable perfmon
For TO1.1 and later: bit0 of GPR11 is enable bit for perfmon.
                     set 1/0 to enable/disable perfmon

add workaround for mx6dl

Signed-off-by: Tony Lin <tony.lin@freescale.com>

diff --git a/arch/arm/plat-mxc/devices/platform-imx-perfmon.c b/arch/arm/plat-mxc/devices/platform-imx-perfmon.c
index 25d1bf582de25ee1cfa4d28b41d8495c71873ba9..518322a8ab66faacb8ca2d11e574336976a6d23b 100644 (file)
--- a/arch/arm/plat-mxc/devices/platform-imx-perfmon.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-perfmon.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -86,8 +86,11 @@ static void platform_perfmon_init(void)
        if (init)
                return;
 
-       /* GPR11 bit[16] is the clock enable bit for perfmon */
-       mxc_iomux_set_gpr_register(11, 16, 1, 1);
+       if (mx6q_revision() == IMX_CHIP_REVISION_1_0)
+               /* GPR11 bit[16] must be set for TO1.0, it's a bug */
+               mxc_iomux_set_gpr_register(11, 16, 1, 1);
+
+       mxc_iomux_set_gpr_register(11, 0, 1, 1);
        init = true;
 }
 
@@ -96,8 +99,7 @@ static void platform_perfmon_exit(void)
        if (!init)
                return;
 
-       /* GPR11 bit[16] is the clock enable bit for perfmon */
-       mxc_iomux_set_gpr_register(11, 16, 1, 0);
+       mxc_iomux_set_gpr_register(11, 0, 1, 0);
        init = false;
 }