From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Tue, 7 Jan 2014 14:14:09 +0000 (+0200)
Subject: drm/i915: Enable watermarks for BDW
X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=03dce881292f43b269f1f8acca69df2c4568ee5c;p=linux-beck.git

drm/i915: Enable watermarks for BDW

We forgot to intialize the watermark vfuncs for BDW, and hence the
watermarks were never updated.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 78503157daf2..835f86386b95 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5627,6 +5627,17 @@ void intel_init_pm(struct drm_device *dev)
 			}
 			dev_priv->display.init_clock_gating = haswell_init_clock_gating;
 		} else if (INTEL_INFO(dev)->gen == 8) {
+			if (dev_priv->wm.pri_latency[0] &&
+			    dev_priv->wm.spr_latency[0] &&
+			    dev_priv->wm.cur_latency[0]) {
+				dev_priv->display.update_wm = ilk_update_wm;
+				dev_priv->display.update_sprite_wm =
+					ilk_update_sprite_wm;
+			} else {
+				DRM_DEBUG_KMS("Failed to read display plane latency. "
+					      "Disable CxSR\n");
+				dev_priv->display.update_wm = NULL;
+			}
 			dev_priv->display.init_clock_gating = gen8_init_clock_gating;
 		} else
 			dev_priv->display.update_wm = NULL;