From: Eric Miao Date: Tue, 29 Jul 2008 06:26:00 +0000 (+0800) Subject: [ARM] pxa: introduce reset_status and clear_reset_status for driver's usage X-Git-Tag: v2.6.27-rc3~67^2~5^2~1 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=04fef228fb00;p=karo-tx-linux.git [ARM] pxa: introduce reset_status and clear_reset_status for driver's usage Due to the problem of reset status bits being handled by different registers between pxa2xx and pxa3xx, introduce a global reset_status variable, initialized by SoC-specific code and later being used by other drivers. And also introduce clear_reset_status(), which is used to clear the corresponding status bits. Pass RESET_STATUS_ALL to clear all bits. Signed-off-by: Eric Miao --- diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index ca053226fba0..36638926c5ce 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c @@ -26,9 +26,19 @@ #include #include +#include #include "generic.h" +void clear_reset_status(unsigned int mask) +{ + if (cpu_is_pxa2xx()) + pxa2xx_clear_reset_status(mask); + + if (cpu_is_pxa3xx()) + pxa3xx_clear_reset_status(mask); +} + /* * Get the clock frequency as reflected by CCCR and the turbo flag. * We assume these values have been applied via a fcs. diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index 5bb7ae757831..041c048320e4 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h @@ -47,12 +47,20 @@ extern unsigned pxa27x_get_memclk_frequency_10khz(void); #define pxa27x_get_memclk_frequency_10khz() (0) #endif +#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) +extern void pxa2xx_clear_reset_status(unsigned int); +#else +static inline void pxa2xx_clear_reset_status(unsigned int mask) {} +#endif + #ifdef CONFIG_PXA3xx extern unsigned pxa3xx_get_clk_frequency_khz(int); extern unsigned pxa3xx_get_memclk_frequency_10khz(void); +extern void pxa3xx_clear_reset_status(unsigned int); #else #define pxa3xx_get_clk_frequency_khz(x) (0) #define pxa3xx_get_memclk_frequency_10khz() (0) +static inline void pxa3xx_clear_reset_status(unsigned int mask) {} #endif extern struct sysdev_class pxa_irq_sysclass; diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index c5b845b935bb..49a7a296ff31 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -348,6 +349,9 @@ static int __init pxa25x_init(void) clks_register(&pxa25x_hwuart_clk, 1); if (cpu_is_pxa21x() || cpu_is_pxa25x()) { + + reset_status = RCSR; + clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks)); if ((ret = pxa_init_dma(16))) diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index d5d14ea33f27..a8c12347a5a9 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -384,6 +385,9 @@ static int __init pxa27x_init(void) int i, ret = 0; if (cpu_is_pxa27x()) { + + reset_status = RCSR; + clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks)); if ((ret = pxa_init_dma(32))) diff --git a/arch/arm/mach-pxa/pxa2xx.c b/arch/arm/mach-pxa/pxa2xx.c index d4f6415e8413..d93d3e6a6e27 100644 --- a/arch/arm/mach-pxa/pxa2xx.c +++ b/arch/arm/mach-pxa/pxa2xx.c @@ -14,10 +14,19 @@ #include #include +#include +#include #include #include +#include #include +void pxa2xx_clear_reset_status(unsigned int mask) +{ + /* RESET_STATUS_* has a 1:1 mapping with RCSR */ + RCSR = mask; +} + static unsigned long pxa2xx_mfp_fir[] = { GPIO46_FICP_RXD, GPIO47_FICP_TXD, diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index f491025a0c82..3d36c790f5ce 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -24,6 +24,7 @@ #include #include +#include #include #include #include @@ -109,6 +110,12 @@ unsigned int pxa3xx_get_memclk_frequency_10khz(void) return (clk / 10000); } +void pxa3xx_clear_reset_status(unsigned int mask) +{ + /* RESET_STATUS_* has a 1:1 mapping with ARSR */ + ARSR = mask; +} + /* * Return the current AC97 clock frequency. */ @@ -532,6 +539,9 @@ static int __init pxa3xx_init(void) int i, ret = 0; if (cpu_is_pxa3xx()) { + + reset_status = ARSR; + /* * clear RDH bit every time after reset * diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c index d610a1244abb..56f60d923a9d 100644 --- a/arch/arm/mach-pxa/reset.c +++ b/arch/arm/mach-pxa/reset.c @@ -11,9 +11,11 @@ #include #include -#include #include +unsigned int reset_status; +EXPORT_SYMBOL(reset_status); + static void do_hw_reset(void); static int reset_gpio = -1; @@ -78,8 +80,7 @@ static void do_hw_reset(void) void arch_reset(char mode) { - if (cpu_is_pxa2xx()) - RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; + clear_reset_status(RESET_STATUS_ALL); switch (mode) { case 's': diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index 0c2fa1c4fb4c..3b6fc090c8ef 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c @@ -31,6 +31,9 @@ #include "generic.h" +unsigned int reset_status; +EXPORT_SYMBOL(reset_status); + #define NR_FREQS 16 /* diff --git a/include/asm-arm/arch-pxa/reset.h b/include/asm-arm/arch-pxa/reset.h index 6ca72c5cf7db..9489a48871a8 100644 --- a/include/asm-arm/arch-pxa/reset.h +++ b/include/asm-arm/arch-pxa/reset.h @@ -1,6 +1,15 @@ #ifndef __ASM_ARCH_RESET_H #define __ASM_ARCH_RESET_H +#define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */ +#define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */ +#define RESET_STATUS_LOWPOWER (1 << 2) /* Low Power/Sleep Exit */ +#define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */ +#define RESET_STATUS_ALL (0xf) + +extern unsigned int reset_status; +extern void clear_reset_status(unsigned int mask); + /* * register GPIO as reset generator */ diff --git a/include/asm-arm/arch-sa1100/reset.h b/include/asm-arm/arch-sa1100/reset.h new file mode 100644 index 000000000000..f61957e6842a --- /dev/null +++ b/include/asm-arm/arch-sa1100/reset.h @@ -0,0 +1,18 @@ +#ifndef __ASM_ARCH_RESET_H +#define __ASM_ARCH_RESET_H + +#include "hardware.h" + +#define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */ +#define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */ +#define RESET_STATUS_LOWPOWER (1 << 2) /* Exit from Low Power/Sleep */ +#define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */ +#define RESET_STATUS_ALL (0xf) + +extern unsigned int reset_status; +static inline void clear_reset_status(unsigned int mask) +{ + RCSR = mask; +} + +#endif /* __ASM_ARCH_RESET_H */