From: Alexander Graf <agraf@suse.de>
Date: Thu, 17 Apr 2014 10:53:13 +0000 (+0200)
Subject: KVM: PPC: E500: Ignore L1CSR1_ICFI,ICLFR
X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=07fec1c2e75ef2f55d7a211414b0d63e185e84f0;p=linux-beck.git

KVM: PPC: E500: Ignore L1CSR1_ICFI,ICLFR

The L1 instruction cache control register contains bits that indicate
that we're still handling a request. Mask those out when we set the SPR
so that a read doesn't assume we're still doing something.

Signed-off-by: Alexander Graf <agraf@suse.de>
---

diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c
index 89b7f821f6c4..95d886f461fb 100644
--- a/arch/powerpc/kvm/e500_emulate.c
+++ b/arch/powerpc/kvm/e500_emulate.c
@@ -222,6 +222,7 @@ int kvmppc_core_emulate_mtspr_e500(struct kvm_vcpu *vcpu, int sprn, ulong spr_va
 		break;
 	case SPRN_L1CSR1:
 		vcpu_e500->l1csr1 = spr_val;
+		vcpu_e500->l1csr1 &= ~(L1CSR1_ICFI | L1CSR1_ICLFR);
 		break;
 	case SPRN_HID0:
 		vcpu_e500->hid0 = spr_val;