From: Tom Rini Date: Fri, 25 Apr 2014 18:53:51 +0000 (-0400) Subject: Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx X-Git-Tag: v2014.07-rc1~15 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=080d897585428d0fd42c237abfb6746908f4effc;hp=-c;p=karo-tx-uboot.git Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx --- 080d897585428d0fd42c237abfb6746908f4effc diff --combined Makefile index 0191869040,00e4b2aa6b..ff38a43857 --- a/Makefile +++ b/Makefile @@@ -740,7 -740,11 +740,11 @@@ ALL-y += u-boot.srec u-boot.bin System. ALL-$(CONFIG_NAND_U_BOOT) += u-boot-nand.bin ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin + ifeq ($(CONFIG_SPL_FSL_PBL),y) + ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin + else ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl + endif ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin @@@ -925,6 -929,21 +929,21 @@@ endi u-boot-img.bin: spl/u-boot-spl.bin u-boot.img FORCE $(call if_changed,cat) + #Add a target to create boot binary having SPL binary in PBI format + #concatenated with u-boot binary. It is need by PowerPC SoC having + #internal SRAM <= 512KB. + MKIMAGEFLAGS_u-boot-spl.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ + -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage + + spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) + + OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \ + --gap-fill=0xff + + u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl u-boot.bin FORCE + $(call if_changed,pad_cat) + # PPC4xx needs the SPL at the end of the image, since the reset vector # is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target # and need to introduce a new build target with the full blown U-Boot @@@ -1093,12 -1112,13 +1112,12 @@@ depend dep @echo '*** Warning: make $@ is unnecessary now.' # --------------------------------------------------------------------------- -define filechk_ubootlds - ($(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \ - -D__ASSEMBLY__ -x assembler-with-cpp -P -o - -) -endef +quiet_cmd_cpp_lds = LDS $@ +cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \ + -D__ASSEMBLY__ -x assembler-with-cpp -P -o $@ $< u-boot.lds: $(LDSCRIPT) prepare FORCE - $(call filechk,ubootlds) + $(call if_changed_dep,cpp_lds) PHONY += nand_spl nand_spl: prepare diff --combined README index f91e0442ad,49dcd37a3c..12758dc6e7 --- a/README +++ b/README @@@ -132,10 -132,6 +132,10 @@@ Directory Hierarchy ==================== /arch Architecture specific files + /arc Files generic to ARC architecture + /cpu CPU specific files + /arc700 Files specific to ARC 700 CPUs + /lib Architecture specific library files /arm Files generic to ARM architecture /cpu CPU specific files /arm720t Files specific to ARM 720 CPUs @@@ -168,7 -164,7 +168,7 @@@ /mips Files generic to MIPS architecture /cpu CPU specific files /mips32 Files specific to MIPS32 CPUs - /xburst Files specific to Ingenic XBurst CPUs + /mips64 Files specific to MIPS64 CPUs /lib Architecture specific library files /nds32 Files generic to NDS32 architecture /cpu CPU specific files @@@ -431,6 -427,14 +431,14 @@@ The following options need to be config In this mode, a single differential clock is used to supply clocks to the sysclock, ddrclock and usbclock. + CONFIG_SYS_CPC_REINIT_F + This CONFIG is defined when the CPC is configured as SRAM at the + time of U-boot entry and is required to be re-initialized. + + CONFIG_DEEP_SLEEP + Inidcates this SoC supports deep sleep feature. If deep sleep is + supported, core will start to execute uboot when wakes up. + - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN @@@ -458,6 -462,9 +466,9 @@@ CONFIG_SYS_FSL_DDRC_GEN3 Freescale DDR3 controller. + CONFIG_SYS_FSL_DDRC_GEN4 + Freescale DDR4 controller. + CONFIG_SYS_FSL_DDRC_ARM_GEN3 Freescale DDR3 controller for ARM-based SoCs. @@@ -473,7 -480,15 +484,15 @@@ CONFIG_SYS_FSL_DDR3 Board config to use DDR3. It can be enabled for SoCs with - Freescale DDR3 controllers. + Freescale DDR3 or DDR3L controllers. + + CONFIG_SYS_FSL_DDR3L + Board config to use DDR3L. It can be enabled for SoCs with + DDR3L controllers. + + CONFIG_SYS_FSL_DDR4 + Board config to use DDR4. It can be enabled for SoCs with + DDR4 controllers. CONFIG_SYS_FSL_IFC_BE Defines the IFC controller register space as Big Endian @@@ -490,6 -505,10 +509,10 @@@ PBI commands can be used to configure SoC before it starts the execution. Please refer doc/README.pblimage for more details + CONFIG_SPL_FSL_PBL + It adds a target to create boot binary having SPL binary in PBI format + concatenated with u-boot binary. + CONFIG_SYS_FSL_DDR_BE Defines the DDR controller register space as Big Endian @@@ -3317,6 -3336,9 +3340,9 @@@ FIT uImage format continuing (the hardware starts execution after just loading the first page rather than the full 4K). + CONFIG_SPL_SKIP_RELOCATE + Avoid SPL relocation + CONFIG_SPL_NAND_BASE Include nand_base.c in the SPL. Requires CONFIG_SPL_NAND_DRIVERS. @@@ -4502,8 -4524,13 +4528,13 @@@ This firmware often needs to be loaded are used to identify the storage device (NOR flash, SPI, etc) and the address within that device. - - CONFIG_SYS_QE_FMAN_FW_ADDR - The address in the storage device where the firmware is located. The + - CONFIG_SYS_FMAN_FW_ADDR + The address in the storage device where the FMAN microcode is located. The + meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro + is also specified. + + - CONFIG_SYS_QE_FW_ADDR + The address in the storage device where the QE microcode is located. The meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro is also specified. diff --combined boards.cfg index f1f699458b,ad34aa72cb..c721ddba21 --- a/boards.cfg +++ b/boards.cfg @@@ -519,6 -519,10 +519,6 @@@ Active mips mips32 au1x Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 - -Active mips mips32 incaip - incaip incaip - Wolfgang Denk -Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk -Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk -Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN - Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN - Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes @@@ -737,10 -741,11 +737,11 @@@ Active powerpc mpc85xx Active powerpc mpc85xx - - socrates socrates - - Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 - - Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - + Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND - Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 - - Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - + Active powerpc mpc85xx - freescale b4860qds B4860QDS_SECURE_BOOT B4860QDS:PPC_B4860,SECURE_BOOT Aneesh Bansal + Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND BSC9131RDB:BSC9131RDB,NAND Poonam Aggrwal @@@ -755,6 -760,14 +756,14 @@@ Active powerpc mpc85xx Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK133 BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133 Naveen Burmi Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100 Naveen Burmi Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi + Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal + Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal + Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal + Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal + Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal + Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal + Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal + Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu @@@ -929,32 -942,46 +938,46 @@@ Active powerpc mpc85xx Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal - Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal - Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal + Active powerpc mpc85xx - freescale t1040qds T1040QDS_D4 T1040QDS:PPC_T1040,SYS_FSL_DDR4 Poonam Aggrwal + Active powerpc mpc85xx - freescale t1040qds T1040QDS_SECURE_BOOT T1040QDS:PPC_T1040,SECURE_BOOT Aneesh Bansal + Active powerpc mpc85xx - freescale t104xrdb T1040RDB T104xRDB:PPC_T1040,T1040RDB Priyanka Jain + Active powerpc mpc85xx - freescale t104xrdb T1040RDB_NAND T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND Priyanka Jain + Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SDCARD T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD + Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SECURE_BOOT T104xRDB:PPC_T1040,SECURE_BOOT,T1040RDB Aneesh Bansal + Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SPIFLASH T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH Priyanka Jain + Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T104xRDB:PPC_T1042,T1042RDB_PI Priyanka Jain + Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_NAND T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND Priyanka Jain + Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_SDCARD T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD + Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_SPIFLASH T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH Priyanka Jain Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080 - - Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - - Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - - Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - + Active powerpc mpc85xx - freescale t208xqds T2080QDS_SECURE_BOOT T208xQDS:PPC_T2080,SECURE_BOOT Aneesh Bansal + Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND + Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD + Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH Active powerpc mpc85xx - freescale t208xqds T2080QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t208xqds T2081QDS T208xQDS:PPC_T2081 - - Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - - Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - - Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - + Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND + Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD - + Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH - Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t208xrdb T2080RDB T208xRDB:PPC_T2080 - - Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - - Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SDCARD T208xRDB:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - - Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SPIFLASH T208xRDB:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - + Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND + Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SDCARD T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD + Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SPIFLASH T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SRIO_PCIE_BOOT T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 - - Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - + Active powerpc mpc85xx - freescale t4qds T4160QDS_SECURE_BOOT T4240QDS:PPC_T4160,SECURE_BOOT Aneesh Bansal + Active powerpc mpc85xx - freescale t4qds T4160QDS_NAND T4240QDS:PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND - + Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD - Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 - - Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - - Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - + Active powerpc mpc85xx - freescale t4qds T4240QDS_SECURE_BOOT T4240QDS:PPC_T4240,SECURE_BOOT Aneesh Bansal + Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND - + Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD - Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - + Active powerpc mpc85xx - freescale qemu-ppce500 qemu-ppce500 - Alexander Graf Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach