From: Michael Chan Date: Mon, 15 Oct 2007 09:12:26 +0000 (-0700) Subject: TG3: Fix performance regression on 5705. X-Git-Tag: v2.6.23.5~10 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=08b37aeea7a8d34367d7a88f66d568d57a8ee3a2;p=karo-tx-linux.git TG3: Fix performance regression on 5705. patch 114342f2d38439cb1a54f1f724fa38729b093c48 in mainline. A performance regression was introduced by the following commit: commit ee6a99b539a50b4e9398938a0a6d37f8bf911550 Author: Michael Chan Date: Wed Jul 18 21:49:10 2007 -0700 [TG3]: Fix msi issue with kexec/kdump. In making that change, the PCI latency timer and cache line size registers were not restored after chip reset. On the 5705, the latency timer gets reset to 0 during chip reset and this causes very poor performance. Update version to 3.81.1 Signed-off-by: Michael Chan Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 9034a05734ef..f80721ecd337 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -64,8 +64,8 @@ #define DRV_MODULE_NAME "tg3" #define PFX DRV_MODULE_NAME ": " -#define DRV_MODULE_VERSION "3.81" -#define DRV_MODULE_RELDATE "September 5, 2007" +#define DRV_MODULE_VERSION "3.81.1" +#define DRV_MODULE_RELDATE "October 18, 2007" #define TG3_DEF_MAC_MODE 0 #define TG3_DEF_RX_MODE 0 @@ -4874,6 +4874,12 @@ static void tg3_restore_pci_state(struct tg3 *tp) pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd); + if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { + pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, + tp->pci_cacheline_sz); + pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, + tp->pci_lat_timer); + } /* Make sure PCI-X relaxed ordering bit is clear. */ pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val); val &= ~PCIX_CAPS_RELAXED_ORDERING;