From: Al Cooper Date: Fri, 13 Jul 2012 20:44:51 +0000 (-0400) Subject: MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt) X-Git-Tag: next-20120817~87^2^3~3 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=0b724c5a224c795c9f380a776778dda94ae5e95e;p=karo-tx-linux.git MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt) The PCI (Program Counter Interrupt) bit in the "cause" register is mandatory for MIPS32R2 cores, but has also been added to some R1 cores (BMIPS5000). This change adds a cpu feature bit to make it easier to check for and use this feature. Signed-off-by: Al Cooper Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/4106/ Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index ca400f7c3f59..55db8e1157f0 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -252,4 +252,8 @@ #define cpu_hwrena_impl_bits 0 #endif +#ifndef cpu_has_perf_cntr_intr_bit +#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI) +#endif + #endif /* __ASM_CPU_FEATURES_H */ diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index f21b7c04e95a..783e5989d389 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -319,6 +319,7 @@ enum cpu_type_enum { #define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ #define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ +#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */ /* * CPU ASE encodings diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 7f87d824eeb0..2b83c36bae48 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -458,6 +458,8 @@ #define CAUSEF_IP7 (_ULCAST_(1) << 15) #define CAUSEB_IV 23 #define CAUSEF_IV (_ULCAST_(1) << 23) +#define CAUSEB_PCI 26 +#define CAUSEF_PCI (_ULCAST_(1) << 26) #define CAUSEB_CE 28 #define CAUSEF_CE (_ULCAST_(3) << 28) #define CAUSEB_TI 30 diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 1b51046191e8..7ae3895d68af 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1186,8 +1186,11 @@ __cpuinit void cpu_probe(void) } } - if (cpu_has_mips_r2) + if (cpu_has_mips_r2) { c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; + /* R2 has Performance Counter Interrupt indicator */ + c->options |= MIPS_CPU_PCI; + } else c->srsets = 1; diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 8451f04627d8..4ee111142aad 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -1158,7 +1158,7 @@ static int mipsxx_pmu_handle_shared_irq(void) int handled = IRQ_NONE; struct pt_regs *regs; - if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26))) + if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI)) return handled; /* * First we pause the local counters, so that when we are locked