From: Pawel Moll <pawel.moll@arm.com>
Date: Fri, 20 May 2011 13:39:29 +0000 (+0100)
Subject: ARM: proc: add Cortex-A5 proc info
X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=15eb169bfec291faf25b158cfa9842b72f7803ad;p=mv-sheeva.git

ARM: proc: add Cortex-A5 proc info

This patch adds processor info for ARM Ltd. Cortex A5,
which has SCU initialisation procedure identical to A9.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index a759ccafeac..3185da27a53 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -278,6 +278,7 @@ cpu_resume_l1_flags:
  *	It is assumed that:
  *	- cache type register is implemented
  */
+__v7_ca5mp_setup:
 __v7_ca9mp_setup:
 #ifdef CONFIG_SMP
 	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
@@ -443,6 +444,16 @@ __v7_setup_stack:
 	.long	v7_cache_fns
 .endm
 
+	/*
+	 * ARM Ltd. Cortex A5 processor.
+	 */
+	.type   __v7_ca5mp_proc_info, #object
+__v7_ca5mp_proc_info:
+	.long	0x410fc050
+	.long	0xff0ffff0
+	__v7_proc __v7_ca5mp_setup
+	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
+
 	/*
 	 * ARM Ltd. Cortex A9 processor.
 	 */