From: Geert Uytterhoeven Date: Mon, 26 Oct 2015 08:43:22 +0000 (+0100) Subject: serial: sh-sci: Update DT binding documentation for BRG support X-Git-Tag: v4.5-rc1~123^2~2^2~23 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=176ae5f674ebd2049f99e97eb8319200f1d211b6;p=karo-tx-linux.git serial: sh-sci: Update DT binding documentation for BRG support Amend the DT bindings to include the optional clock sources for the Baud Rate Generator for External Clock (BRG), as found on some SCIF variants and on HSCIF. Signed-off-by: Geert Uytterhoeven Acked-by: Greg Kroah-Hartman --- diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index 31cc0631ef7c..f4ad30ef1628 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -56,6 +56,12 @@ Required properties: On (H)SCI(F) and some SCIFA, an additional clock may be specified: - "hsck" for the optional external clock input (on HSCIF), - "sck" for the optional external clock input (on other variants). + On UARTs equipped with a Baud Rate Generator for External Clock (BRG) + (some SCIF and HSCIF), additional clocks may be specified: + - "brg_int" for the optional internal clock source for the frequency + divider (typically the (AXI or SHwy) bus clock), + - "scif_clk" for the optional external clock source for the frequency + divider (SCIF_CLK). Note: Each enabled SCIx UART should have an alias correctly numbered in the "aliases" node.