From: Arnd Bergmann <arnd@arndb.de>
Date: Tue, 26 Apr 2016 08:02:03 +0000 (+0200)
Subject: Merge tag 'renesas-fixes-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git... 
X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=20bef320366f13b81a21c198dd33c14084ee6cc3;p=linux-beck.git

Merge tag 'renesas-fixes-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Renesas ARM Based SoC Fixes for v4.6

* Correct preset_lpj calculation which may lead to too short delays
* Correct handling of optional clocks on r8a7791 to restore
  access to the serial port the porter board

This is a backmerge of v4.6 fixes, to avoid a merge conflict between 4.6
and our next/dt branch.

* tag 'renesas-fixes-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: timer: Fix preset_lpj leading to too short delays
  Revert "ARM: dts: porter: Enable SCIF_CLK frequency and pins"
  ARM: dts: r8a7791: Don't disable referenced optional clocks
---

20bef320366f13b81a21c198dd33c14084ee6cc3
diff --cc arch/arm/boot/dts/r8a7791-porter.dts
index 9554d13362f6,a9285d9a57cd..6a1bb1a8209b
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@@ -142,22 -143,14 +142,14 @@@
  };
  
  &pfc {
- 	pinctrl-0 = <&scif_clk_pins>;
- 	pinctrl-names = "default";
- 
  	scif0_pins: serial0 {
 -		renesas,groups = "scif0_data_d";
 -		renesas,function = "scif0";
 +		groups = "scif0_data_d";
 +		function = "scif0";
  	};
  
- 	scif_clk_pins: scif_clk {
- 		groups = "scif_clk";
- 		function = "scif_clk";
- 	};
- 
  	ether_pins: ether {
 -		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
 -		renesas,function = "eth";
 +		groups = "eth_link", "eth_mdio", "eth_rmii";
 +		function = "eth";
  	};
  
  	phy1_pins: phy1 {
diff --cc arch/arm/boot/dts/r8a7791.dtsi
index 6d4a0b6e4df9,1cd1b6a3a72a..565c270e549d
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@@ -1076,11 -1079,12 +1076,10 @@@
  		};
  
  		/* External PCIe clock - can be overridden by the board */
 -		pcie_bus_clk: pcie_bus_clk {
 +		pcie_bus_clk: pcie_bus {
  			compatible = "fixed-clock";
  			#clock-cells = <0>;
- 			clock-frequency = <100000000>;
- 			status = "disabled";
+ 			clock-frequency = <0>;
 -			clock-output-names = "pcie_bus";
  		};
  
  		/* External SCIF clock */
@@@ -1105,7 -1109,7 +1103,6 @@@
  			#clock-cells = <0>;
  			/* This value must be overridden by the board. */
  			clock-frequency = <0>;
- 			status = "disabled";
 -			clock-output-names = "can_clk";
  		};
  
  		/* Special CPG clocks */