From: Ville Syrjälä Date: Wed, 8 Jul 2015 20:45:47 +0000 (+0300) Subject: drm/i915: Always program m2 fractional value on CHV X-Git-Tag: KARO-TX6UL-2015-11-03~85^2~19^2~95 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=25a25dfce4e678bb18c4d63937d240839ecd19cd;p=karo-tx-linux.git drm/i915: Always program m2 fractional value on CHV When fractional m2 divider isn't used on CHV the fractional part is ignore by the hardware. Despite that, program the fractional value (0 in this case) to the hardware register just to keep things a bit more consistent. Might at least make register dumps a bit less confusing when there isn't some stale fractional part hanging around. Signed-off-by: Ville Syrjälä Reviewed-by: Deepak S Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index cf8dfa53e338..a64da67b4f40 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7374,8 +7374,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc, 1 << DPIO_CHV_N_DIV_SHIFT); /* M2 fraction division */ - if (bestm2_frac) - vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); + vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); /* M2 fraction division enable */ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));