From: Shawn Guo Date: Wed, 10 Jul 2013 03:06:17 +0000 (+0800) Subject: ARM: dts: add more pin groups for imx6q/dl X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=28da9c854d950f06ee7f5929c2e13cbc5b0833b6;p=karo-tx-linux.git ARM: dts: add more pin groups for imx6q/dl The patch adds pin groups that are already defined by community kernel, so that both kernels can align on the pin group label names. Signed-off-by: Shawn Guo --- diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 62dc78126795..277e52fc1730 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -37,6 +37,54 @@ compatible = "fsl,imx6dl-iomuxc"; reg = <0x020e0000 0x4000>; + audmux { + pinctrl_audmux_1: audmux-1 { + fsl,pins = < + MX6DL_PAD_SD2_DAT0__AUD4_RXD 0x80000000 + MX6DL_PAD_SD2_DAT3__AUD4_TXC 0x80000000 + MX6DL_PAD_SD2_DAT2__AUD4_TXD 0x80000000 + MX6DL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000 + >; + }; + + pinctrl_audmux_2: audmux-2 { + fsl,pins = < + MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 + MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 + MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 + MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 + >; + }; + }; + + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + >; + }; + + pinctrl_ecspi1_2: ecspi1grp-2 { + fsl,pins = < + MX6DL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6DL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + >; + }; + }; + + ecspi3 { + pinctrl_ecspi3_1: ecspi3grp-1 { + fsl,pins = < + MX6DL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6DL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6DL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + >; + }; + }; + enet { pinctrl_enet_1: enetgrp-1 { fsl,pins = < @@ -78,6 +126,92 @@ MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 >; }; + + pinctrl_enet_3: enetgrp-3 { + fsl,pins = < + MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6DL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + >; + }; + }; + + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + }; + + i2c1 { + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX6DL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6DL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX6DL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6DL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_2: i2c2grp-2 { + fsl,pins = < + MX6DL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6DL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + }; + + i2c3 { + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX6DL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6DL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; }; uart1 { @@ -89,6 +223,24 @@ }; }; + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + MX6DL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6DL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2_2: uart2grp-2 { /* DTE mode */ + fsl,pins = < + MX6DL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6DL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6DL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 + MX6DL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + >; + }; + }; + uart4 { pinctrl_uart4_1: uart4grp-1 { fsl,pins = < @@ -99,6 +251,12 @@ }; usbotg { + pinctrl_usbotg_1: usbotggrp-1 { + fsl,pins = < + MX6DL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + pinctrl_usbotg_2: usbotggrp-2 { fsl,pins = < MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 @@ -121,6 +279,17 @@ MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059 >; }; + + pinctrl_usdhc2_2: usdhc2grp-2 { + fsl,pins = < + MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; }; usdhc3 { @@ -139,7 +308,7 @@ >; }; - pinctrl_usdhc3_2: usdhc3grp_2 { + pinctrl_usdhc3_2: usdhc3grp-2 { fsl,pins = < MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059 MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059 @@ -151,7 +320,91 @@ }; }; + usdhc4 { + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + MX6DL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6DL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6DL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6DL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6DL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6DL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6DL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6DL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6DL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6DL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + pinctrl_usdhc4_2: usdhc4grp-2 { + fsl,pins = < + MX6DL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6DL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6DL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6DL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6DL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6DL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + >; + }; + }; + + weim { + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX6DL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor_1: weim_norgrp-1 { + fsl,pins = < + MX6DL_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6DL_PAD_EIM_RW__EIM_RW 0xb0b1 + MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 + /* data */ + MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 + MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 + MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 + MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 + MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 + MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 + MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 + MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 + MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 + MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 + MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 + MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 + MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 + MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 + MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 + MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 + /* address */ + MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 + MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 + MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 + MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 + MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 + MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 + MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 + MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 + MX6DL_PAD_EIM_DA15__EIM_AD15 0xb0b1 + MX6DL_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6DL_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6DL_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6DL_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6DL_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6DL_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6DL_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6DL_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6DL_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6DL_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6DL_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6DL_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6DL_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6DL_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6DL_PAD_EIM_DA0__EIM_AD00 0xb0b1 + >; + }; + }; }; pxp: pxp@020f0000 { diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index dc54a72a3bcd..e0b7bad7f78f 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -108,6 +108,14 @@ MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 >; }; + + pinctrl_ecspi1_2: ecspi1grp-2 { + fsl,pins = < + MX6Q_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + >; + }; }; ecspi3 { @@ -161,6 +169,27 @@ MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 >; }; + + pinctrl_enet_3: enetgrp-3 { + fsl,pins = < + MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + >; + }; }; gpmi-nand { @@ -172,8 +201,6 @@ MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000 MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1 - MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1 MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1 MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1 MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1 @@ -196,6 +223,13 @@ MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 >; }; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; }; i2c2 { @@ -232,6 +266,15 @@ MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 >; }; + + pinctrl_uart2_2: uart2grp-2 { /* DTE mode */ + fsl,pins = < + MX6Q_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6Q_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6Q_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 + MX6Q_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + >; + }; }; uart4 { @@ -272,6 +315,17 @@ MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059 >; }; + + pinctrl_usdhc2_2: usdhc2grp-2 { + fsl,pins = < + MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; }; usdhc3 { @@ -329,6 +383,64 @@ >; }; }; + + weim { + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX6Q_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor_1: weim_norgrp-1 { + fsl,pins = < + MX6Q_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6Q_PAD_EIM_RW__EIM_RW 0xb0b1 + MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 + /* data */ + MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0 + MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0 + MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0 + MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0 + MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0 + MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0 + MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0 + MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0 + MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0 + MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0 + MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0 + MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0 + MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0 + MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0 + MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0 + MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0 + /* address */ + MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1 + MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1 + MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1 + MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1 + MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1 + MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1 + MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1 + MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1 + MX6Q_PAD_EIM_DA15__EIM_AD15 0xb0b1 + MX6Q_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6Q_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6Q_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6Q_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6Q_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6Q_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6Q_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6Q_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6Q_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6Q_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6Q_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6Q_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6Q_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6Q_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6Q_PAD_EIM_DA0__EIM_AD00 0xb0b1 + >; + }; + }; }; };