From: Elaine Zhang <zhangqing@rock-chips.com>
Date: Wed, 17 May 2017 10:16:14 +0000 (+0800)
Subject: ARM: dts: rockchip: set default rates for core clocks on rk322x
X-Git-Tag: v4.13-rc1~168^2~23^2~10
X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=30ee58146b53d83e90fc5326488e1e48a5a3aba4;p=karo-tx-linux.git

ARM: dts: rockchip: set default rates for core clocks on rk322x

Set sane default frequencies for CPLL, GPLL and some other core clocks
on the rk322x.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---

diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 816b0796d816..c256df9a2cd8 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -346,8 +346,18 @@
 		rockchip,grf = <&grf>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
-		assigned-clocks = <&cru PLL_GPLL>;
-		assigned-clock-rates = <594000000>;
+		assigned-clocks =
+			<&cru PLL_GPLL>, <&cru ARMCLK>,
+			<&cru PLL_CPLL>, <&cru ACLK_PERI>,
+			<&cru HCLK_PERI>, <&cru PCLK_PERI>,
+			<&cru ACLK_CPU>, <&cru HCLK_CPU>,
+			<&cru PCLK_CPU>;
+		assigned-clock-rates =
+			<594000000>, <816000000>,
+			<500000000>, <150000000>,
+			<150000000>, <75000000>,
+			<150000000>, <150000000>,
+			<75000000>;
 	};
 
 	thermal-zones {