From: Russell King Date: Thu, 6 Jan 2011 22:33:32 +0000 (+0000) Subject: Merge branch 'devel-stable' into devel X-Git-Tag: v2.6.38-rc1~471^2 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=404a02cbd2ae8bf256a2fa1169bdfe86bb5ebb34;hp=-c;p=karo-tx-linux.git Merge branch 'devel-stable' into devel Conflicts: arch/arm/mach-pxa/clock.c arch/arm/mach-pxa/clock.h --- 404a02cbd2ae8bf256a2fa1169bdfe86bb5ebb34 diff --combined arch/arm/Kconfig index 32cbf3e888ff,fac58916adec..a3fb23be87f3 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@@ -2,7 -2,6 +2,7 @@@ config AR bool default y select HAVE_AOUT + select HAVE_DMA_API_DEBUG select HAVE_IDE select HAVE_MEMBLOCK select RTC_LIB @@@ -25,7 -24,6 +25,7 @@@ select PERF_USE_VMALLOC select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7)) + select HAVE_C_RECORDMCOUNT help The ARM series is a line of low-power-consumption RISC chip designs licensed by ARM Ltd and targeted at embedded applications and @@@ -37,15 -35,9 +37,15 @@@ config HAVE_PWM bool +config MIGHT_HAVE_PCI + bool + config SYS_SUPPORTS_APM_EMULATION bool +config HAVE_SCHED_CLOCK + bool + config GENERIC_GPIO bool @@@ -230,7 -222,7 +230,7 @@@ config ARCH_INTEGRATO bool "ARM Ltd. Integrator family" select ARM_AMBA select ARCH_HAS_CPUFREQ - select COMMON_CLKDEV + select CLKDEV_LOOKUP select ICST select GENERIC_CLOCKEVENTS select PLAT_VERSATILE @@@ -240,8 -232,7 +240,8 @@@ config ARCH_REALVIEW bool "ARM Ltd. RealView family" select ARM_AMBA - select COMMON_CLKDEV + select CLKDEV_LOOKUP + select HAVE_SCHED_CLOCK select ICST select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB @@@ -255,8 -246,7 +255,8 @@@ config ARCH_VERSATIL bool "ARM Ltd. Versatile family" select ARM_AMBA select ARM_VIC - select COMMON_CLKDEV + select CLKDEV_LOOKUP + select HAVE_SCHED_CLOCK select ICST select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB @@@ -270,10 -260,9 +270,10 @@@ config ARCH_VEXPRES select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_AMBA select ARM_TIMER_SP804 - select COMMON_CLKDEV + select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS select HAVE_CLK + select HAVE_SCHED_CLOCK select ICST select PLAT_VERSATILE help @@@ -292,7 -281,7 +292,7 @@@ config ARCH_BCMRIN depends on MMU select CPU_V6 select ARM_AMBA - select COMMON_CLKDEV + select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB help @@@ -310,7 -299,6 +310,7 @@@ config ARCH_CNS3XX select CPU_V6 select GENERIC_CLOCKEVENTS select ARM_GIC + select MIGHT_HAVE_PCI select PCI_DOMAINS if PCI help Support for Cavium Networks CNS3XXX platform. @@@ -340,7 -328,7 +340,7 @@@ config ARCH_EP93X select CPU_ARM920T select ARM_AMBA select ARM_VIC - select COMMON_CLKDEV + select CLKDEV_LOOKUP select ARCH_REQUIRE_GPIOLIB select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_USES_GETTIMEOFFSET @@@ -360,14 -348,22 +360,22 @@@ config ARCH_MX bool "Freescale MXC/iMX-based" select GENERIC_CLOCKEVENTS select ARCH_REQUIRE_GPIOLIB - select COMMON_CLKDEV + select CLKDEV_LOOKUP help Support for Freescale MXC/iMX-based family of processors + config ARCH_MXS + bool "Freescale MXS-based" + select GENERIC_CLOCKEVENTS + select ARCH_REQUIRE_GPIOLIB + select COMMON_CLKDEV + help + Support for Freescale MXS-based family of processors + config ARCH_STMP3XXX bool "Freescale STMP3xxx" select CPU_ARM926T - select COMMON_CLKDEV + select CLKDEV_LOOKUP select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS select USB_ARCH_HAS_EHCI @@@ -446,8 -442,6 +454,8 @@@ config ARCH_IXP4X select CPU_XSCALE select GENERIC_GPIO select GENERIC_CLOCKEVENTS + select HAVE_SCHED_CLOCK + select MIGHT_HAVE_PCI select DMABOUNCE if PCI help Support for Intel's IXP4XX (XScale) family of processors. @@@ -487,7 -481,7 +495,7 @@@ config ARCH_LPC32X select HAVE_IDE select ARM_AMBA select USB_ARCH_HAS_OHCI - select COMMON_CLKDEV + select CLKDEV_LOOKUP select GENERIC_TIME select GENERIC_CLOCKEVENTS help @@@ -521,9 -515,8 +529,9 @@@ config ARCH_MM bool "Marvell PXA168/910/MMP2" depends on MMU select ARCH_REQUIRE_GPIOLIB - select COMMON_CLKDEV + select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS + select HAVE_SCHED_CLOCK select TICK_ONESHOT select PLAT_PXA select SPARSE_IRQ @@@ -555,7 -548,7 +563,7 @@@ config ARCH_W90X90 bool "Nuvoton W90X900 CPU" select CPU_ARM926T select ARCH_REQUIRE_GPIOLIB - select COMMON_CLKDEV + select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS help Support for Nuvoton (Winbond logic dept.) ARM9 processor, @@@ -569,19 -562,18 +577,19 @@@ config ARCH_NUC93X bool "Nuvoton NUC93X CPU" select CPU_ARM926T - select COMMON_CLKDEV + select CLKDEV_LOOKUP help Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a low-power and high performance MPEG-4/JPEG multimedia controller chip. config ARCH_TEGRA bool "NVIDIA Tegra" + select CLKDEV_LOOKUP select GENERIC_TIME select GENERIC_CLOCKEVENTS select GENERIC_GPIO select HAVE_CLK - select COMMON_CLKDEV + select HAVE_SCHED_CLOCK select ARCH_HAS_BARRIERS if CACHE_L2X0 select ARCH_HAS_CPUFREQ help @@@ -591,7 -583,7 +599,7 @@@ config ARCH_PNX4008 bool "Philips Nexperia PNX4008 Mobile" select CPU_ARM926T - select COMMON_CLKDEV + select CLKDEV_LOOKUP select ARCH_USES_GETTIMEOFFSET help This enables support for Philips PNX4008 mobile platform. @@@ -601,10 -593,9 +609,10 @@@ config ARCH_PX depends on MMU select ARCH_MTD_XIP select ARCH_HAS_CPUFREQ - select COMMON_CLKDEV + select CLKDEV_LOOKUP select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS + select HAVE_SCHED_CLOCK select TICK_ONESHOT select PLAT_PXA select SPARSE_IRQ @@@ -653,7 -644,6 +661,7 @@@ config ARCH_SA110 select CPU_FREQ select GENERIC_CLOCKEVENTS select HAVE_CLK + select HAVE_SCHED_CLOCK select TICK_ONESHOT select ARCH_REQUIRE_GPIOLIB help @@@ -780,7 -770,7 +788,7 @@@ config ARCH_TCC_92 bool "Telechips TCC ARM926-based systems" select CPU_ARM926T select HAVE_CLK - select COMMON_CLKDEV + select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS help Support for Telechips TCC ARM926-based systems. @@@ -800,12 -790,11 +808,12 @@@ config ARCH_U30 bool "ST-Ericsson U300 Series" depends on MMU select CPU_ARM926T + select HAVE_SCHED_CLOCK select HAVE_TCM select ARM_AMBA select ARM_VIC select GENERIC_CLOCKEVENTS - select COMMON_CLKDEV + select CLKDEV_LOOKUP select GENERIC_GPIO help Support for ST-Ericsson U300 series mobile platforms. @@@ -815,8 -804,9 +823,9 @@@ config ARCH_U850 select CPU_V7 select ARM_AMBA select GENERIC_CLOCKEVENTS - select COMMON_CLKDEV + select CLKDEV_LOOKUP select ARCH_REQUIRE_GPIOLIB + select ARCH_HAS_CPUFREQ help Support for ST-Ericsson's Ux500 architecture @@@ -825,7 -815,7 +834,7 @@@ config ARCH_NOMADI select ARM_AMBA select ARM_VIC select CPU_ARM926T - select COMMON_CLKDEV + select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS select ARCH_REQUIRE_GPIOLIB help @@@ -837,7 -827,7 +846,7 @@@ config ARCH_DAVINC select ARCH_REQUIRE_GPIOLIB select ZONE_DMA select HAVE_IDE - select COMMON_CLKDEV + select CLKDEV_LOOKUP select GENERIC_ALLOCATOR select ARCH_HAS_HOLES_MEMORYMODEL help @@@ -849,7 -839,6 +858,7 @@@ config ARCH_OMA select ARCH_REQUIRE_GPIOLIB select ARCH_HAS_CPUFREQ select GENERIC_CLOCKEVENTS + select HAVE_SCHED_CLOCK select ARCH_HAS_HOLES_MEMORYMODEL help Support for TI's OMAP platform (OMAP1/2/3/4). @@@ -858,7 -847,7 +867,7 @@@ config PLAT_SPEA bool "ST SPEAr" select ARM_AMBA select ARCH_REQUIRE_GPIOLIB - select COMMON_CLKDEV + select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS select HAVE_CLK help @@@ -923,6 -912,8 +932,8 @@@ source "arch/arm/mach-mv78xx0/Kconfig source "arch/arm/plat-mxc/Kconfig" + source "arch/arm/mach-mxs/Kconfig" + source "arch/arm/mach-netx/Kconfig" source "arch/arm/mach-nomadik/Kconfig" @@@ -1003,11 -994,9 +1014,11 @@@ config ARCH_ACOR config PLAT_IOP bool select GENERIC_CLOCKEVENTS + select HAVE_SCHED_CLOCK config PLAT_ORION bool + select HAVE_SCHED_CLOCK config PLAT_PXA bool @@@ -1022,8 -1011,8 +1033,8 @@@ source arch/arm/mm/Kconfi config IWMMXT bool "Enable iWMMXt support" - depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK - default y if PXA27x || PXA3xx || ARCH_MMP + depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 + default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP help Enable support for iWMMXt context switching at run time if running on a CPU that supports it. @@@ -1040,11 -1029,6 +1051,11 @@@ config CPU_HAS_PM default y bool +config MULTI_IRQ_HANDLER + bool + help + Allow each machine to specify it's own IRQ handler at run time. + if !MMU source "arch/arm/Kconfig-nommu" endif @@@ -1192,7 -1176,7 +1203,7 @@@ config ISA_DMA_AP bool config PCI - bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX + bool "PCI support" if MIGHT_HAVE_PCI help Find out whether you have a PCI motherboard. PCI is the name of a bus system, i.e. the way the CPU talks to the other stuff inside @@@ -1203,12 -1187,6 +1214,12 @@@ config PCI_DOMAIN bool depends on PCI +config PCI_NANOENGINE + bool "BSE nanoEngine PCI support" + depends on SA1100_NANOENGINE + help + Enable PCI on the BSE nanoEngine board. + config PCI_SYSCALL def_bool PCI @@@ -1264,7 -1242,7 +1275,7 @@@ config SM config SMP_ON_UP bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" depends on EXPERIMENTAL - depends on SMP && !XIP && !THUMB2_KERNEL + depends on SMP && !XIP default y help SMP kernels contain instructions which fail on non-SMP processors. @@@ -1283,7 -1261,6 +1294,7 @@@ config HAVE_ARM_SC config HAVE_ARM_TWD bool depends on SMP + select TICK_ONESHOT help This options enables support for the ARM timer and watchdog unit @@@ -1347,7 -1324,7 +1358,7 @@@ config H default 100 config THUMB2_KERNEL - bool "Compile the kernel in Thumb-2 mode" + bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)" depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL select AEABI select ARM_ASM_UNIFIED @@@ -1561,7 -1538,6 +1572,7 @@@ config SECCOM config CC_STACKPROTECTOR bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" + depends on EXPERIMENTAL help This option turns on the -fstack-protector GCC feature. This feature puts, at the beginning of functions, a canary value on @@@ -1688,19 -1664,6 +1699,19 @@@ config ATAGS_PRO Should the atags used to boot the kernel be exported in an "atags" file in procfs. Useful with kexec. +config CRASH_DUMP + bool "Build kdump crash kernel (EXPERIMENTAL)" + depends on EXPERIMENTAL + help + Generate crash dump after being started by kexec. This should + be normally only set in special crash dump kernels which are + loaded in the main kernel with kexec-tools into a specially + reserved region and then later executed after a crash by + kdump/kexec. The crash dump kernel must be compiled to a + memory address not used by the main kernel + + For more details see Documentation/kdump/kdump.txt + config AUTO_ZRELADDR bool "Auto calculation of the decompressed kernel image address" depends on !ZBOOT_ROM && !ARCH_U300 @@@ -1758,7 -1721,7 +1769,7 @@@ config CPU_FREQ_S3 Internal configuration node for common cpufreq on Samsung SoC config CPU_FREQ_S3C24XX - bool "CPUfreq driver for Samsung S3C24XX series CPUs" + bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL select CPU_FREQ_S3C help @@@ -1770,7 -1733,7 +1781,7 @@@ If in doubt, say N. config CPU_FREQ_S3C24XX_PLL - bool "Support CPUfreq changing of PLL frequency" + bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" depends on CPU_FREQ_S3C24XX && EXPERIMENTAL help Compile in support for changing the PLL frequency from the diff --combined arch/arm/kernel/Makefile index 7c33e6f29bcc,c73abe4b7e72..185ee822c935 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@@ -29,8 -29,7 +29,8 @@@ obj-$(CONFIG_MODULES) += armksyms.o mo obj-$(CONFIG_ARTHUR) += arthur.o obj-$(CONFIG_ISA_DMA) += dma-isa.o obj-$(CONFIG_PCI) += bios32.o isa.o -obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_HAVE_SCHED_CLOCK) += sched_clock.o +obj-$(CONFIG_SMP) += smp.o smp_tlb.o obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o obj-$(CONFIG_HAVE_ARM_TWD) += smp_twd.o obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o @@@ -44,8 -43,6 +44,8 @@@ obj-$(CONFIG_KGDB) += kgdb. obj-$(CONFIG_ARM_UNWIND) += unwind.o obj-$(CONFIG_HAVE_TCM) += tcm.o obj-$(CONFIG_CRASH_DUMP) += crash_dump.o +obj-$(CONFIG_SWP_EMULATE) += swp_emulate.o +CFLAGS_swp_emulate.o := -Wa,-march=armv7-a obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o @@@ -54,6 -51,7 +54,7 @@@ AFLAGS_crunch-bits.o := -Wa,-mcpu=ep93 obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o + obj-$(CONFIG_CPU_PJ4) += pj4-cp0.o obj-$(CONFIG_IWMMXT) += iwmmxt.o obj-$(CONFIG_CPU_HAS_PMU) += pmu.o obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o diff --combined arch/arm/kernel/entry-armv.S index 27f64489c1cb,36199ffc4cc2..2b46fea36c9f --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@@ -25,22 -25,42 +25,22 @@@ #include #include "entry-header.S" +#include /* * Interrupt handling. Preserves r7, r8, r9 */ .macro irq_handler - get_irqnr_preamble r5, lr -1: get_irqnr_and_base r0, r6, r5, lr - movne r1, sp - @ - @ routine called with r0 = irq number, r1 = struct pt_regs * - @ - adrne lr, BSYM(1b) - bne asm_do_IRQ - -#ifdef CONFIG_SMP - /* - * XXX - * - * this macro assumes that irqstat (r6) and base (r5) are - * preserved from get_irqnr_and_base above - */ - ALT_SMP(test_for_ipi r0, r6, r5, lr) - ALT_UP_B(9997f) - movne r0, sp - adrne lr, BSYM(1b) - bne do_IPI - -#ifdef CONFIG_LOCAL_TIMERS - test_for_ltirq r0, r6, r5, lr - movne r0, sp - adrne lr, BSYM(1b) - bne do_local_timer +#ifdef CONFIG_MULTI_IRQ_HANDLER + ldr r5, =handle_arch_irq + mov r0, sp + ldr r5, [r5] + adr lr, BSYM(9997f) + teq r5, #0 + movne pc, r5 #endif + arch_irq_handler_default 9997: -#endif - .endm #ifdef CONFIG_KPROBES @@@ -178,6 -198,7 +178,7 @@@ __dabt_svc @ @ set desired IRQ state, then call main handler @ + debug_entry r1 msr cpsr_c, r9 mov r2, sp bl do_DataAbort @@@ -304,6 -325,7 +305,7 @@@ __pabt_svc #else bl CPU_PABORT_HANDLER #endif + debug_entry r1 msr cpsr_c, r9 @ Maybe enable interrupts mov r2, sp @ regs bl do_PrefetchAbort @ call abort handler @@@ -419,6 -441,7 +421,7 @@@ __dabt_usr @ @ IRQs on, then call the main handler @ + debug_entry r1 enable_irq mov r2, sp adr lr, BSYM(ret_from_exception) @@@ -683,6 -706,7 +686,7 @@@ __pabt_usr #else bl CPU_PABORT_HANDLER #endif + debug_entry r1 enable_irq @ Enable interrupts mov r2, sp @ regs bl do_PrefetchAbort @ call abort handler @@@ -715,7 -739,7 +719,7 @@@ ENTRY(__switch_to THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack THUMB( str sp, [ip], #4 ) THUMB( str lr, [ip], #4 ) -#ifdef CONFIG_MMU +#ifdef CONFIG_CPU_USE_DOMAINS ldr r6, [r2, #TI_CPU_DOMAIN] #endif set_tls r3, r4, r5 @@@ -724,7 -748,7 +728,7 @@@ ldr r8, =__stack_chk_guard ldr r7, [r7, #TSK_STACK_CANARY] #endif -#ifdef CONFIG_MMU +#ifdef CONFIG_CPU_USE_DOMAINS mcr p15, 0, r6, c3, c0, 0 @ Set domain register #endif mov r5, r0 @@@ -822,7 -846,7 +826,7 @@@ __kuser_helper_start */ __kuser_memory_barrier: @ 0xffff0fa0 - smp_dmb + smp_dmb arm usr_ret lr .align 5 @@@ -939,7 -963,7 +943,7 @@@ kuser_cmpxchg_fixup #else - smp_dmb + smp_dmb arm 1: ldrex r3, [r2] subs r3, r3, r0 strexeq r3, r1, [r2] @@@ -1225,9 -1249,3 +1229,9 @@@ cr_alignment .space 4 cr_no_alignment: .space 4 + +#ifdef CONFIG_MULTI_IRQ_HANDLER + .globl handle_arch_irq +handle_arch_irq: + .space 4 +#endif diff --combined arch/arm/mach-cns3xxx/core.h index ef9e5116b1a9,73898a7835d3..ffeb3a8b73ba --- a/arch/arm/mach-cns3xxx/core.h +++ b/arch/arm/mach-cns3xxx/core.h @@@ -11,12 -11,11 +11,10 @@@ #ifndef __CNS3XXX_CORE_H #define __CNS3XXX_CORE_H -extern void __iomem *gic_cpu_base_addr; extern struct sys_timer cns3xxx_timer; void __init cns3xxx_map_io(void); void __init cns3xxx_init_irq(void); void cns3xxx_power_off(void); - void cns3xxx_pwr_power_up(unsigned int block); - void cns3xxx_pwr_power_down(unsigned int block); #endif /* __CNS3XXX_CORE_H */ diff --combined arch/arm/mach-davinci/time.c index c1486716de77,5d1eea026635..e1969ce904dc --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c @@@ -272,13 -272,35 +272,34 @@@ static cycle_t read_cycles(struct clock return (cycles_t)timer32_read(t); } + /* + * Kernel assumes that sched_clock can be called early but may not have + * things ready yet. + */ + static cycle_t read_dummy(struct clocksource *cs) + { + return 0; + } + + static struct clocksource clocksource_davinci = { .rating = 300, - .read = read_cycles, + .read = read_dummy, .mask = CLOCKSOURCE_MASK(32), - .shift = 24, .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; + /* + * Overwrite weak default sched_clock with something more precise + */ + unsigned long long notrace sched_clock(void) + { + const cycle_t cyc = clocksource_davinci.read(&clocksource_davinci); + + return clocksource_cyc2ns(cyc, clocksource_davinci.mult, + clocksource_davinci.shift); + } + /* * clockevent */ @@@ -376,9 -398,12 +397,10 @@@ static void __init davinci_timer_init(v davinci_clock_tick_rate = clk_get_rate(timer_clk); /* setup clocksource */ + clocksource_davinci.read = read_cycles; clocksource_davinci.name = id_to_name[clocksource_id]; - clocksource_davinci.mult = - clocksource_khz2mult(davinci_clock_tick_rate/1000, - clocksource_davinci.shift); - if (clocksource_register(&clocksource_davinci)) + if (clocksource_register_hz(&clocksource_davinci, + davinci_clock_tick_rate)) printk(err, clocksource_davinci.name); /* setup clockevent */ diff --combined arch/arm/mach-imx/clock-imx21.c index d7056559715a,c63a4f5ffcb6..bf30a8c7ce6f --- a/arch/arm/mach-imx/clock-imx21.c +++ b/arch/arm/mach-imx/clock-imx21.c @@@ -21,11 -21,11 +21,11 @@@ #include #include #include +#include #include #include #include -#include #include #define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off))) @@@ -1185,7 -1185,7 +1185,7 @@@ static struct clk_lookup lookups[] = _REGISTER_CLOCK(NULL, "brom", brom_clk) _REGISTER_CLOCK(NULL, "emma", emma_clk[0]) _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0]) - _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) + _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk) _REGISTER_CLOCK(NULL, "gpio", gpio_clk) _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk) diff --combined arch/arm/mach-imx/clock-imx25.c index 00dcb08019e9,21ef34c501e5..daa0165b6772 --- a/arch/arm/mach-imx/clock-imx25.c +++ b/arch/arm/mach-imx/clock-imx25.c @@@ -21,7 -21,8 +21,7 @@@ #include #include #include - -#include +#include #include #include @@@ -295,7 -296,7 +295,7 @@@ static struct clk_lookup lookups[] = _REGISTER_CLOCK("fec.0", NULL, fec_clk) _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk) _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) - _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk) + _REGISTER_CLOCK("imx2-wdt.0", NULL, wdt_clk) _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) diff --combined arch/arm/mach-imx/clock-imx27.c index ca1017b9028d,f32f3b8e8ba4..583f2515c1d5 --- a/arch/arm/mach-imx/clock-imx27.c +++ b/arch/arm/mach-imx/clock-imx27.c @@@ -21,8 -21,8 +21,8 @@@ #include #include #include +#include -#include #include #include @@@ -125,7 -125,7 +125,7 @@@ static int clk_cpu_set_parent(struct cl if (clk->parent == parent) return 0; - if (mx27_revision() >= CHIP_REV_2_0) { + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { if (parent == &mpll_main1_clk) { cscr |= CCM_CSCR_ARM_SRC; } else { @@@ -174,7 -174,7 +174,7 @@@ static int set_rate_cpu(struct clk *clk div--; reg = __raw_readl(CCM_CSCR); - if (mx27_revision() >= CHIP_REV_2_0) { + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { reg &= ~(3 << 12); reg |= div << 12; reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN); @@@ -244,7 -244,7 +244,7 @@@ static unsigned long get_rate_ssix(stru parent_rate = clk_get_rate(clk->parent); - if (mx27_revision() >= CHIP_REV_2_0) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) pdf += 4; /* MX27 TO2+ */ else pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */ @@@ -269,7 -269,7 +269,7 @@@ static unsigned long get_rate_nfc(struc parent_rate = clk_get_rate(clk->parent); - if (mx27_revision() >= CHIP_REV_2_0) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf; else nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf; @@@ -284,7 -284,7 +284,7 @@@ static unsigned long get_rate_vpu(struc parent_rate = clk_get_rate(clk->parent); - if (mx27_revision() >= CHIP_REV_2_0) { + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f; vpu_pdf += 4; } else { @@@ -347,7 -347,7 +347,7 @@@ static unsigned long get_rate_mpll_main * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2 * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3 */ - if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0 && clk->id == 1) return 2UL * parent_rate / 3UL; return parent_rate; @@@ -365,7 -365,7 +365,7 @@@ static unsigned long get_rate_spll(stru /* On TO2 we have to write the value back. Otherwise we * read 0 from this register the next time. */ - if (mx27_revision() >= CHIP_REV_2_0) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) __raw_writel(reg, CCM_SPCTL0); return mxc_decode_pll(reg, rate); @@@ -376,7 -376,7 +376,7 @@@ static unsigned long get_rate_cpu(struc u32 div; unsigned long rate; - if (mx27_revision() >= CHIP_REV_2_0) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) div = (__raw_readl(CCM_CSCR) >> 12) & 0x3; else div = (__raw_readl(CCM_CSCR) >> 13) & 0x7; @@@ -389,7 -389,7 +389,7 @@@ static unsigned long get_rate_ahb(struc { unsigned long rate, bclk_pdf; - if (mx27_revision() >= CHIP_REV_2_0) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3; else bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf; @@@ -402,7 -402,7 +402,7 @@@ static unsigned long get_rate_ipg(struc { unsigned long rate, ipg_pdf; - if (mx27_revision() >= CHIP_REV_2_0) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) return clk_get_rate(clk->parent); else ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1; @@@ -667,7 -667,7 +667,7 @@@ static struct clk_lookup lookups[] = _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk) _REGISTER_CLOCK(NULL, "ata", ata_clk) _REGISTER_CLOCK(NULL, "mstick", mstick_clk) - _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) + _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk) _REGISTER_CLOCK(NULL, "gpio", gpio_clk) _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) @@@ -683,7 -683,7 +683,7 @@@ static void __init to2_adjust_clocks(vo { unsigned long cscr = __raw_readl(CCM_CSCR); - if (mx27_revision() >= CHIP_REV_2_0) { + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { if (cscr & CCM_CSCR_ARM_SRC) cpu_clk.parent = &mpll_main1_clk; diff --combined arch/arm/mach-mx3/clock-imx31.c index 1cd8b40b7676,4193cf5a2637..d423cac8cab7 --- a/arch/arm/mach-mx3/clock-imx31.c +++ b/arch/arm/mach-mx3/clock-imx31.c @@@ -23,8 -23,8 +23,8 @@@ #include #include #include +#include -#include #include #include @@@ -530,7 -530,7 +530,7 @@@ static struct clk_lookup lookups[] = _REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk) _REGISTER_CLOCK(NULL, "gpt", gpt_clk) _REGISTER_CLOCK(NULL, "pwm", pwm_clk) - _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) + _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk) _REGISTER_CLOCK(NULL, "rtc", rtc_clk) _REGISTER_CLOCK(NULL, "epit", epit1_clk) _REGISTER_CLOCK(NULL, "epit", epit2_clk) @@@ -615,7 -615,7 +615,7 @@@ int __init mx31_clocks_init(unsigned lo mx31_read_cpu_rev(); - if (mx31_revision() >= MX31_CHIP_REV_2_0) { + if (mx31_revision() >= IMX_CHIP_REVISION_2_0) { reg = __raw_readl(MXC_CCM_PMCR1); /* No PLL restart on DVFS switch; enable auto EMI handshake */ reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN; diff --combined arch/arm/mach-mx3/clock-imx35.c index 819dd809615a,22259d955837..448a038cd1ec --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c @@@ -21,7 -21,8 +21,7 @@@ #include #include #include - -#include +#include #include #include @@@ -494,7 -495,7 +494,7 @@@ static struct clk_lookup lookups[] = _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk) - _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) + _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk) _REGISTER_CLOCK(NULL, "max", max_clk) _REGISTER_CLOCK(NULL, "audmux", audmux_clk) _REGISTER_CLOCK(NULL, "csi", csi_clk) diff --combined arch/arm/mach-mx5/clock-mx51-mx53.c index 5975edb47de8,b21bc47d4827..785e1a336183 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@@ -14,8 -14,8 +14,8 @@@ #include #include #include +#include -#include #include #include @@@ -33,11 -33,15 +33,15 @@@ static struct clk pll1_main_clk static struct clk pll1_sw_clk; static struct clk pll2_sw_clk; static struct clk pll3_sw_clk; + static struct clk mx53_pll4_sw_clk; static struct clk lp_apm_clk; static struct clk periph_apm_clk; static struct clk ahb_clk; static struct clk ipg_clk; static struct clk usboh3_clk; + static struct clk emi_fast_clk; + static struct clk ipu_clk; + static struct clk mipi_hsc1_clk; #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ @@@ -123,7 -127,7 +127,7 @@@ static inline u32 _get_mux(struct clk * return -EINVAL; } - static inline void __iomem *_get_pll_base(struct clk *pll) + static inline void __iomem *_mx51_get_pll_base(struct clk *pll) { if (pll == &pll1_main_clk) return MX51_DPLL1_BASE; @@@ -137,6 -141,30 +141,30 @@@ return NULL; } + static inline void __iomem *_mx53_get_pll_base(struct clk *pll) + { + if (pll == &pll1_main_clk) + return MX53_DPLL1_BASE; + else if (pll == &pll2_sw_clk) + return MX53_DPLL2_BASE; + else if (pll == &pll3_sw_clk) + return MX53_DPLL3_BASE; + else if (pll == &mx53_pll4_sw_clk) + return MX53_DPLL4_BASE; + else + BUG(); + + return NULL; + } + + static inline void __iomem *_get_pll_base(struct clk *pll) + { + if (cpu_is_mx51()) + return _mx51_get_pll_base(pll); + else + return _mx53_get_pll_base(pll); + } + static unsigned long clk_pll_get_rate(struct clk *clk) { long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; @@@ -514,7 -542,10 +542,10 @@@ static int _clk_max_enable(struct clk * /* Handshake with MAX when LPM is entered. */ reg = __raw_readl(MXC_CCM_CLPCR); - reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + if (cpu_is_mx51()) + reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS; + else if (cpu_is_mx53()) + reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS; __raw_writel(reg, MXC_CCM_CLPCR); return 0; @@@ -528,7 -559,10 +559,10 @@@ static void _clk_max_disable(struct cl /* No Handshake with MAX when LPM is entered as its disabled. */ reg = __raw_readl(MXC_CCM_CLPCR); - reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + if (cpu_is_mx51()) + reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS; + else if (cpu_is_mx53()) + reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS; __raw_writel(reg, MXC_CCM_CLPCR); } @@@ -679,6 -713,19 +713,19 @@@ static unsigned long clk_emi_slow_get_r return clk_get_rate(clk->parent) / div; } + static unsigned long _clk_ddr_hf_get_rate(struct clk *clk) + { + unsigned long rate; + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >> + MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1; + rate = clk_get_rate(clk->parent) / div; + + return rate; + } + /* External high frequency clock */ static struct clk ckih_clk = { .get_rate = get_high_reference_clock_rate, @@@ -739,6 -786,14 +786,14 @@@ static struct clk pll3_sw_clk = .disable = _clk_pll_disable, }; + /* PLL4 SW supplies to LVDS Display Bridge(LDB) */ + static struct clk mx53_pll4_sw_clk = { + .parent = &osc_clk, + .set_rate = _clk_pll_set_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + }; + /* Low-power Audio Playback Mode clock */ static struct clk lp_apm_clk = { .parent = &osc_clk, @@@ -763,6 -818,12 +818,12 @@@ static struct clk ahb_clk = .round_rate = _clk_ahb_round_rate, }; + static struct clk iim_clk = { + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, + }; + /* Main IP interface clock for access to registers */ static struct clk ipg_clk = { .parent = &ahb_clk, @@@ -810,6 -871,10 +871,10 @@@ static struct clk kpp_clk = .id = 0, }; + static struct clk dummy_clk = { + .id = 0, + }; + static struct clk emi_slow_clk = { .parent = &pll2_sw_clk, .enable_reg = MXC_CCM_CCGR5, @@@ -819,6 -884,109 +884,109 @@@ .get_rate = clk_emi_slow_get_rate, }; + static int clk_ipu_enable(struct clk *clk) + { + u32 reg; + + _clk_ccgr_enable(clk); + + /* Enable handshake with IPU when certain clock rates are changed */ + reg = __raw_readl(MXC_CCM_CCDR); + reg &= ~MXC_CCM_CCDR_IPU_HS_MASK; + __raw_writel(reg, MXC_CCM_CCDR); + + /* Enable handshake with IPU when LPM is entered */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + + return 0; + } + + static void clk_ipu_disable(struct clk *clk) + { + u32 reg; + + _clk_ccgr_disable(clk); + + /* Disable handshake with IPU whe dividers are changed */ + reg = __raw_readl(MXC_CCM_CCDR); + reg |= MXC_CCM_CCDR_IPU_HS_MASK; + __raw_writel(reg, MXC_CCM_CCDR); + + /* Disable handshake with IPU when LPM is entered */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + } + + static struct clk ahbmux1_clk = { + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable_inwait, + }; + + static struct clk ipu_sec_clk = { + .parent = &emi_fast_clk, + .secondary = &ahbmux1_clk, + }; + + static struct clk ddr_hf_clk = { + .parent = &pll1_sw_clk, + .get_rate = _clk_ddr_hf_get_rate, + }; + + static struct clk ddr_clk = { + .parent = &ddr_hf_clk, + }; + + /* clock definitions for MIPI HSC unit which has been removed + * from documentation, but not from hardware + */ + static int _clk_hsc_enable(struct clk *clk) + { + u32 reg; + + _clk_ccgr_enable(clk); + /* Handshake with IPU when certain clock rates are changed. */ + reg = __raw_readl(MXC_CCM_CCDR); + reg &= ~MXC_CCM_CCDR_HSC_HS_MASK; + __raw_writel(reg, MXC_CCM_CCDR); + + reg = __raw_readl(MXC_CCM_CLPCR); + reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + + return 0; + } + + static void _clk_hsc_disable(struct clk *clk) + { + u32 reg; + + _clk_ccgr_disable(clk); + /* No handshake with HSC as its not enabled. */ + reg = __raw_readl(MXC_CCM_CCDR); + reg |= MXC_CCM_CCDR_HSC_HS_MASK; + __raw_writel(reg, MXC_CCM_CCDR); + + reg = __raw_readl(MXC_CCM_CLPCR); + reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + } + + static struct clk mipi_hsp_clk = { + .parent = &ipu_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .enable = _clk_hsc_enable, + .disable = _clk_hsc_disable, + .secondary = &mipi_hsc1_clk, + }; + #define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s) \ static struct clk name = { \ .id = i, \ @@@ -927,6 -1095,41 +1095,41 @@@ static struct clk usboh3_clk = .parent = &pll2_sw_clk, .get_rate = clk_usboh3_get_rate, .set_parent = clk_usboh3_set_parent, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, + }; + + static struct clk usb_ahb_clk = { + .parent = &ipg_clk, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + }; + + static int clk_usb_phy1_set_parent(struct clk *clk, struct clk *parent) + { + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; + + if (parent == &pll3_sw_clk) + reg |= 1 << MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET; + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; + } + + static struct clk usb_phy1_clk = { + .parent = &pll3_sw_clk, + .set_parent = clk_usb_phy1_set_parent, + .enable = _clk_ccgr_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .disable = _clk_ccgr_disable, }; /* eCSPI */ @@@ -1013,6 -1216,10 +1216,10 @@@ DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_C NULL, NULL, &ipg_clk, NULL); DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET, NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk); + DEFINE_CLOCK(ssi3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG12_OFFSET, + NULL, NULL, &ipg_clk, NULL); + DEFINE_CLOCK(ssi3_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG13_OFFSET, + NULL, NULL, &pll3_sw_clk, &ssi3_ipg_clk); /* eCSPI */ DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET, @@@ -1046,6 -1253,23 +1253,23 @@@ DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MX DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET, clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk); + DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk); + DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk); + DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk); + + /* IPU */ + DEFINE_CLOCK_FULL(ipu_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG5_OFFSET, + NULL, NULL, clk_ipu_enable, clk_ipu_disable, &ahb_clk, &ipu_sec_clk); + + DEFINE_CLOCK_FULL(emi_fast_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG7_OFFSET, + NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable_inwait, + &ddr_clk, NULL); + + DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET, + NULL, NULL, &pll3_sw_clk, NULL); + DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET, + NULL, NULL, &pll3_sw_clk, NULL); + #define _REGISTER_CLOCK(d, n, c) \ { \ .dev_id = d, \ @@@ -1053,7 -1277,7 +1277,7 @@@ .clk = &c, \ }, - static struct clk_lookup lookups[] = { + static struct clk_lookup mx51_lookups[] = { _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) @@@ -1063,15 -1287,19 +1287,19 @@@ _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk) _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk) - _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk) + _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk) + _REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy1_clk) _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk) - _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk) + _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk) + _REGISTER_CLOCK("mxc-ehci.2", "usb", usboh3_clk) + _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk) _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk) _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) + _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk) _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk) _REGISTER_CLOCK(NULL, "ckih", ckih_clk) _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk) @@@ -1082,6 -1310,22 +1310,22 @@@ _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk) + _REGISTER_CLOCK(NULL, "iim_clk", iim_clk) + _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk) + _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk) + _REGISTER_CLOCK(NULL, "mipi_hsp", mipi_hsp_clk) + _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk) + _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk) + _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk) + }; + + static struct clk_lookup mx53_lookups[] = { + _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) + _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) + _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) + _REGISTER_CLOCK(NULL, "gpt", gpt_clk) + _REGISTER_CLOCK("fec.0", NULL, fec_clk) + _REGISTER_CLOCK(NULL, "iim_clk", iim_clk) }; static void clk_tree_init(void) @@@ -1114,14 -1358,22 +1358,22 @@@ int __init mx51_clocks_init(unsigned lo ckih2_reference = ckih2; oscillator_reference = osc; - for (i = 0; i < ARRAY_SIZE(lookups); i++) - clkdev_add(&lookups[i]); + for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++) + clkdev_add(&mx51_lookups[i]); clk_tree_init(); + clk_set_parent(&uart_root_clk, &pll3_sw_clk); clk_enable(&cpu_clk); clk_enable(&main_bus_clk); + clk_enable(&iim_clk); + mx51_revision(); + clk_disable(&iim_clk); + + /* move usb_phy_clk to 24MHz */ + clk_set_parent(&usb_phy1_clk, &osc_clk); + /* set the usboh3_clk parent to pll2_sw_clk */ clk_set_parent(&usboh3_clk, &pll2_sw_clk); @@@ -1138,3 -1390,31 +1390,31 @@@ MX51_MXC_INT_GPT); return 0; } + + int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2) + { + int i; + + external_low_reference = ckil; + external_high_reference = ckih1; + ckih2_reference = ckih2; + oscillator_reference = osc; + + for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++) + clkdev_add(&mx53_lookups[i]); + + clk_tree_init(); + + clk_enable(&cpu_clk); + clk_enable(&main_bus_clk); + + clk_enable(&iim_clk); + mx53_revision(); + clk_disable(&iim_clk); + + /* System timer */ + mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), + MX53_INT_GPT); + return 0; + } diff --combined arch/arm/mach-pxa/Kconfig index c98d81ff250c,1df6db6a136e..2fc9f94cdd29 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@@ -50,6 -50,10 +50,10 @@@ config MACH_SAA select PXA3xx select CPU_PXA930 + config MACH_SAARB + bool "PXA955 Handheld Platform (aka SAARB)" + select CPU_PXA955 + comment "Third Party Dev Platforms (sorted by vendor name)" config ARCH_PXA_IDP @@@ -94,7 -98,6 +98,7 @@@ config MACH_ARMCOR select PXA27x select IWMMXT select PXA25x + select MIGHT_HAVE_PCI config MACH_EM_X270 bool "CompuLab EM-x270 platform" @@@ -233,10 -236,6 +237,6 @@@ config MACH_COLIBR bool "Toradex Colibri PXA270" select PXA27x - config MACH_COLIBRI_PXA270_EVALBOARD - bool "Toradex Colibri Evaluation Carrier Board support (PXA270)" - depends on MACH_COLIBRI - config MACH_COLIBRI_PXA270_INCOME bool "Income s.r.o. PXA270 SBC" depends on MACH_COLIBRI @@@ -254,6 -253,10 +254,10 @@@ config MACH_COLIBRI32 select PXA3xx select CPU_PXA320 + config MACH_COLIBRI_EVALBOARD + bool "Toradex Colibri Evaluation Carrier Board support" + depends on MACH_COLIBRI || MACH_COLIBRI300 || MACH_COLIBRI320 + config MACH_VPAC270 bool "Voipac PXA270" select PXA27x @@@ -541,7 -544,6 +545,7 @@@ config MACH_ICONTRO config ARCH_PXA_ESERIES bool "PXA based Toshiba e-series PDAs" select PXA25x + select FB_W100 config MACH_E330 bool "Toshiba e330" @@@ -653,11 -655,17 +657,17 @@@ config CPU_PXA93 help PXA935 (codename Tavor-P65) - config CPU_PXA950 + config PXA95x bool - select CPU_PXA930 + select CPU_PJ4 + help + Select code specific to PXA95x variants + + config CPU_PXA955 + bool + select PXA95x help - PXA950 (codename Tavor-PV2) + PXA950 (codename MG1) config PXA_SHARP_C7xx bool diff --combined arch/arm/mach-pxa/clock.c index 4e4a84be96ba,8184fe2d71c3..d5152220ce94 --- a/arch/arm/mach-pxa/clock.c +++ b/arch/arm/mach-pxa/clock.c @@@ -3,21 -3,12 +3,11 @@@ */ #include #include - #include - #include - #include - #include #include #include - #include #include - -#include +#include - #include - #include - - #include "devices.h" - #include "generic.h" #include "clock.h" static DEFINE_SPINLOCK(clocks_lock); @@@ -63,18 -54,19 +53,19 @@@ unsigned long clk_get_rate(struct clk * } EXPORT_SYMBOL(clk_get_rate); - - void clk_cken_enable(struct clk *clk) + void clk_dummy_enable(struct clk *clk) { - CKEN |= 1 << clk->cken; } - void clk_cken_disable(struct clk *clk) + void clk_dummy_disable(struct clk *clk) { - CKEN &= ~(1 << clk->cken); } - const struct clkops clk_cken_ops = { - .enable = clk_cken_enable, - .disable = clk_cken_disable, + const struct clkops clk_dummy_ops = { + .enable = clk_dummy_enable, + .disable = clk_dummy_disable, + }; + + struct clk clk_dummy = { + .ops = &clk_dummy_ops, }; diff --combined arch/arm/mach-pxa/clock.h index 12cc0e87e6c4,6e949944f2ec..f9f349a21b54 --- a/arch/arm/mach-pxa/clock.h +++ b/arch/arm/mach-pxa/clock.h @@@ -1,4 -1,5 +1,5 @@@ +#include + #include -#include struct clkops { void (*enable)(struct clk *); @@@ -14,6 -15,12 +15,12 @@@ struct clk unsigned int enabled; }; + void clk_dummy_enable(struct clk *); + void clk_dummy_disable(struct clk *); + + extern const struct clkops clk_dummy_ops; + extern struct clk clk_dummy; + #define INIT_CLKREG(_clk,_devname,_conname) \ { \ .clk = _clk, \ @@@ -21,14 -28,6 +28,6 @@@ .con_id = _conname, \ } - #define DEFINE_CKEN(_name, _cken, _rate, _delay) \ - struct clk clk_##_name = { \ - .ops = &clk_cken_ops, \ - .rate = _rate, \ - .cken = CKEN_##_cken, \ - .delay = _delay, \ - } - #define DEFINE_CK(_name, _cken, _ops) \ struct clk clk_##_name = { \ .ops = _ops, \ @@@ -42,28 -41,38 +41,38 @@@ struct clk clk_##_name = { .delay = _delay, \ } - extern const struct clkops clk_cken_ops; - - void clk_cken_enable(struct clk *clk); - void clk_cken_disable(struct clk *clk); - - #ifdef CONFIG_PXA3xx - #define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay) \ + #define DEFINE_PXA2_CKEN(_name, _cken, _rate, _delay) \ struct clk clk_##_name = { \ - .ops = &clk_pxa3xx_cken_ops, \ + .ops = &clk_pxa2xx_cken_ops, \ .rate = _rate, \ .cken = CKEN_##_cken, \ .delay = _delay, \ } - #define DEFINE_PXA3_CK(_name, _cken, _ops) \ + extern const struct clkops clk_pxa2xx_cken_ops; + + void clk_pxa2xx_cken_enable(struct clk *clk); + void clk_pxa2xx_cken_disable(struct clk *clk); + + extern struct sysdev_class pxa2xx_clock_sysclass; + + #if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x) + #define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay) \ struct clk clk_##_name = { \ - .ops = _ops, \ + .ops = &clk_pxa3xx_cken_ops, \ + .rate = _rate, \ .cken = CKEN_##_cken, \ + .delay = _delay, \ } extern const struct clkops clk_pxa3xx_cken_ops; + extern const struct clkops clk_pxa3xx_hsio_ops; + extern const struct clkops clk_pxa3xx_ac97_ops; + extern const struct clkops clk_pxa3xx_pout_ops; + extern const struct clkops clk_pxa3xx_smemc_ops; + extern void clk_pxa3xx_cken_enable(struct clk *); extern void clk_pxa3xx_cken_disable(struct clk *); - #endif + extern struct sysdev_class pxa3xx_clock_sysclass; + #endif diff --combined arch/arm/mach-pxa/sleep.S index ae008110db4e,2f5b08aeb52e..c551da86baf6 --- a/arch/arm/mach-pxa/sleep.S +++ b/arch/arm/mach-pxa/sleep.S @@@ -14,7 -14,7 +14,7 @@@ #include #include #include - + #include #include #define MDREFR_KDIV 0x200a4000 // all banks @@@ -353,8 -353,8 +353,8 @@@ resume_turn_on_mmu @ Let us ensure we jump to resume_after_mmu only when the mcr above @ actually took effect. They call it the "cpwait" operation. - mrc p15, 0, r1, c2, c0, 0 @ queue a dependency on CP15 - sub pc, r2, r1, lsr #32 @ jump to virtual addr + mrc p15, 0, r0, c2, c0, 0 @ queue a dependency on CP15 + sub pc, r2, r0, lsr #32 @ jump to virtual addr nop nop nop diff --combined arch/arm/mach-ux500/clock.c index 531de5c63641,912d1cc18c57..ccff2dae167f --- a/arch/arm/mach-ux500/clock.c +++ b/arch/arm/mach-ux500/clock.c @@@ -13,12 -13,19 +13,18 @@@ #include #include #include - -#include +#include #include #include #include "clock.h" + #ifdef CONFIG_DEBUG_FS + #include + #include /* for copy_from_user */ + static LIST_HEAD(clk_list); + #endif + #define PRCC_PCKEN 0x00 #define PRCC_PCKDIS 0x04 #define PRCC_KCKEN 0x08 @@@ -132,7 -139,7 +138,7 @@@ static unsigned long clk_mtu_get_rate(s { void __iomem *addr = __io_address(UX500_PRCMU_BASE) + PRCM_TCR; - u32 tcr = readl(addr); + u32 tcr; int mtu = (int) clk->data; /* * One of these is selected eventually @@@ -143,6 -150,14 +149,14 @@@ unsigned long mturate; unsigned long retclk; + /* + * On a startup, always conifgure the TCR to the doze mode; + * bootloaders do it for us. Do this in the kernel too. + */ + writel(PRCM_TCR_DOZE_MODE, addr); + + tcr = readl(addr); + /* Get the rate from the parent as a default */ if (clk->parent_periph) mturate = clk_get_rate(clk->parent_periph); @@@ -152,45 -167,6 +166,6 @@@ /* We need to be connected SOMEWHERE */ BUG(); - /* - * Are we in doze mode? - * In this mode the parent peripheral or the fixed 32768 Hz - * clock is fed into the block. - */ - if (!(tcr & PRCM_TCR_DOZE_MODE)) { - /* - * Here we're using the clock input from the APE ULP - * clock domain. But first: are the timers stopped? - */ - if (tcr & PRCM_TCR_STOPPED) { - clk32k = 0; - mturate = 0; - } else { - /* Else default mode: 0 and 2.4 MHz */ - clk32k = 0; - if (cpu_is_u5500()) - /* DB5500 divides by 8 */ - mturate /= 8; - else if (cpu_is_u8500ed()) { - /* - * This clocking setting must not be used - * in the ED chip, it is simply not - * connected anywhere! - */ - mturate = 0; - BUG(); - } else - /* - * In this mode the ulp38m4 clock is divided - * by a factor 16, on the DB8500 typically - * 38400000 / 16 ~ 2.4 MHz. - * TODO: Replace the constant with a reference - * to the ULP source once this is modeled. - */ - mturate = 38400000 / 16; - } - } - /* Return the clock selected for this MTU */ if (tcr & (1 << mtu)) retclk = clk32k; @@@ -316,6 -292,7 +291,7 @@@ static struct clkops clk_prcc_ops = }; static struct clk clk_32khz = { + .name = "clk_32khz", .rate = 32000, }; @@@ -365,94 -342,96 +341,96 @@@ static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1 */ /* Peripheral Cluster #1 */ - static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); + static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); - static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); - static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL); - static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL); - static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk); + static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); + static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL); + static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL); + static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk); static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk); - static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk); - static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk); - static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk); - static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk); - static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk); - static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk); + static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk); + static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk); + static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk); + static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk); + static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk); + static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk); /* Peripheral Cluster #2 */ static DEFINE_PRCC_CLK(2, gpio1_ed, 12, -1, NULL); - static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL); - static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL); - static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL); - static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk); - static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk); - static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk); - static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk); + static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL); + static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL); + static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL); + static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk); + static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk); + static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk); + static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk); static DEFINE_PRCC_CLK(2, pwl_ed, 3, 1, NULL); - static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL); - static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL); - static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk); + static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL); + static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL); + static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk); static DEFINE_PRCC_CLK(2, gpio1_v1, 11, -1, NULL); - static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL); - static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL); - static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL); - static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk); - static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk); - static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk); - static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk); + static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL); + static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL); + static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL); + static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk); + static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk); + static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk); + static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk); static DEFINE_PRCC_CLK(2, pwl_v1, 3, 1, NULL); - static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL); - static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL); - static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk); + static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL); + static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL); + static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk); /* Peripheral Cluster #3 */ - static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL); - static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk); - static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk); - static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz); - static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk); - static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk); - static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk); - static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk); - static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk); - static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk); - static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL); + static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL); + static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk); + static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk); + static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz); + static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk); + static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk); + static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk); + static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk); + static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk); + static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk); + static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL); /* Peripheral Cluster #4 is in the always on domain */ /* Peripheral Cluster #5 */ - static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL); - static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk); - static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL); + static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL); + static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk); + static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL); /* Peripheral Cluster #6 */ /* MTU ID in data */ static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1); static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0); - static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL); - static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL); - static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL); - static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk); - static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL); - static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL); - static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL); - static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL); - static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk); - static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk); + static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL); + static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL); + static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL); + static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk); + static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL); + static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL); + static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL); + static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL); + static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk); + static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk); /* Peripheral Cluster #7 */ - static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL); + static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL); /* MTU ID in data */ static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1); static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0); - static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL); - static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL); + static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL); + static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL); - static struct clk clk_dummy_apb_pclk; + static struct clk clk_dummy_apb_pclk = { + .name = "apb_pclk", + }; static struct clk_lookup u8500_common_clks[] = { CLK(dummy_apb_pclk, NULL, "apb_pclk"), @@@ -553,7 -532,7 +531,7 @@@ static struct clk_lookup u8500_ed_clks[ static struct clk_lookup u8500_v1_clks[] = { /* Peripheral Cluster #1 */ - CLK(i2c4, "nmk-i2c.4", NULL), + CLK(i2c4, "nmk-i2c.4", NULL), CLK(spi3_v1, "spi3", NULL), CLK(msp1_v1, "msp1", NULL), @@@ -598,6 -577,183 +576,183 @@@ CLK(uiccclk, "uicc", NULL), }; + #ifdef CONFIG_DEBUG_FS + /* + * debugfs support to trace clock tree hierarchy and attributes with + * powerdebug + */ + static struct dentry *clk_debugfs_root; + + void __init clk_debugfs_add_table(struct clk_lookup *cl, size_t num) + { + while (num--) { + /* Check that the clock has not been already registered */ + if (!(cl->clk->list.prev != cl->clk->list.next)) + list_add_tail(&cl->clk->list, &clk_list); + + cl++; + } + } + + static ssize_t usecount_dbg_read(struct file *file, char __user *buf, + size_t size, loff_t *off) + { + struct clk *clk = file->f_dentry->d_inode->i_private; + char cusecount[128]; + unsigned int len; + + len = sprintf(cusecount, "%u\n", clk->enabled); + return simple_read_from_buffer(buf, size, off, cusecount, len); + } + + static ssize_t rate_dbg_read(struct file *file, char __user *buf, + size_t size, loff_t *off) + { + struct clk *clk = file->f_dentry->d_inode->i_private; + char crate[128]; + unsigned int rate; + unsigned int len; + + rate = clk_get_rate(clk); + len = sprintf(crate, "%u\n", rate); + return simple_read_from_buffer(buf, size, off, crate, len); + } + + static const struct file_operations usecount_fops = { + .read = usecount_dbg_read, + }; + + static const struct file_operations set_rate_fops = { + .read = rate_dbg_read, + }; + + static struct dentry *clk_debugfs_register_dir(struct clk *c, + struct dentry *p_dentry) + { + struct dentry *d, *clk_d, *child, *child_tmp; + char s[255]; + char *p = s; + + if (c->name == NULL) + p += sprintf(p, "BUG"); + else + p += sprintf(p, "%s", c->name); + + clk_d = debugfs_create_dir(s, p_dentry); + if (!clk_d) + return NULL; + + d = debugfs_create_file("usecount", S_IRUGO, + clk_d, c, &usecount_fops); + if (!d) + goto err_out; + d = debugfs_create_file("rate", S_IRUGO, + clk_d, c, &set_rate_fops); + if (!d) + goto err_out; + /* + * TODO : not currently available in ux500 + * d = debugfs_create_x32("flags", S_IRUGO, clk_d, (u32 *)&c->flags); + * if (!d) + * goto err_out; + */ + + return clk_d; + + err_out: + d = clk_d; + list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child) + debugfs_remove(child); + debugfs_remove(clk_d); + return NULL; + } + + static void clk_debugfs_remove_dir(struct dentry *cdentry) + { + struct dentry *d, *child, *child_tmp; + + d = cdentry; + list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child) + debugfs_remove(child); + debugfs_remove(cdentry); + return ; + } + + static int clk_debugfs_register_one(struct clk *c) + { + struct clk *pa = c->parent_periph; + struct clk *bpa = c->parent_cluster; + + if (!(bpa && !pa)) { + c->dent = clk_debugfs_register_dir(c, + pa ? pa->dent : clk_debugfs_root); + if (!c->dent) + return -ENOMEM; + } + + if (bpa) { + c->dent_bus = clk_debugfs_register_dir(c, + bpa->dent_bus ? bpa->dent_bus : bpa->dent); + if ((!c->dent_bus) && (c->dent)) { + clk_debugfs_remove_dir(c->dent); + c->dent = NULL; + return -ENOMEM; + } + } + return 0; + } + + static int clk_debugfs_register(struct clk *c) + { + int err; + struct clk *pa = c->parent_periph; + struct clk *bpa = c->parent_cluster; + + if (pa && (!pa->dent && !pa->dent_bus)) { + err = clk_debugfs_register(pa); + if (err) + return err; + } + + if (bpa && (!bpa->dent && !bpa->dent_bus)) { + err = clk_debugfs_register(bpa); + if (err) + return err; + } + + if ((!c->dent) && (!c->dent_bus)) { + err = clk_debugfs_register_one(c); + if (err) + return err; + } + return 0; + } + + static int __init clk_debugfs_init(void) + { + struct clk *c; + struct dentry *d; + int err; + + d = debugfs_create_dir("clock", NULL); + if (!d) + return -ENOMEM; + clk_debugfs_root = d; + + list_for_each_entry(c, &clk_list, list) { + err = clk_debugfs_register(c); + if (err) + goto err_out; + } + return 0; + err_out: + debugfs_remove_recursive(clk_debugfs_root); + return err; + } + + late_initcall(clk_debugfs_init); + #endif /* defined(CONFIG_DEBUG_FS) */ + int __init clk_init(void) { if (cpu_is_u8500ed()) { @@@ -608,7 -764,8 +763,8 @@@ /* Clock tree for U5500 not implemented yet */ clk_prcc_ops.enable = clk_prcc_ops.disable = NULL; clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL; - clk_per6clk.rate = 26000000; + clk_uartclk.rate = 36360000; + clk_sdmmcclk.rate = 99900000; } clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); @@@ -617,5 -774,12 +773,12 @@@ else clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks)); + #ifdef CONFIG_DEBUG_FS + clk_debugfs_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); + if (cpu_is_u8500ed()) + clk_debugfs_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks)); + else + clk_debugfs_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks)); + #endif return 0; } diff --combined arch/arm/mach-ux500/cpu.c index 7328c0179769,a3700bc374d3..5730409c0f7d --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@@ -6,7 -6,6 +6,6 @@@ */ #include - #include #include #include @@@ -20,6 -19,7 +19,7 @@@ #include #include #include + #include #include "clock.h" @@@ -45,29 -45,22 +45,22 @@@ static struct map_desc ux500_io_desc[] __IO_DEV_DESC(UX500_BACKUPRAM0_BASE, SZ_8K), }; - static struct amba_device *ux500_amba_devs[] __initdata = { - &ux500_pl031_device, - }; - void __init ux500_map_io(void) { iotable_init(ux500_io_desc, ARRAY_SIZE(ux500_io_desc)); } - void __init ux500_init_devices(void) - { - amba_add_devices(ux500_amba_devs, ARRAY_SIZE(ux500_amba_devs)); - } - void __init ux500_init_irq(void) { - gic_dist_init(0, __io_address(UX500_GIC_DIST_BASE), 29); - gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE)); + gic_init(0, 29, __io_address(UX500_GIC_DIST_BASE), + __io_address(UX500_GIC_CPU_BASE)); /* * Init clocks here so that they are available for system timer * initialization. */ + if (cpu_is_u8500()) + prcmu_early_init(); clk_init(); } diff --combined arch/arm/mach-ux500/platsmp.c index 2115a0cf07b0,ade2e17f253c..d77e76cb7edd --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@@ -18,6 -18,7 +18,6 @@@ #include #include -#include #include #include @@@ -25,37 -26,31 +25,37 @@@ * control for which core is the next to come out of the secondary * boot "holding pen" */ - volatile int __cpuinitdata pen_release = -1; + volatile int pen_release = -1; -static unsigned int __init get_core_count(void) +/* + * Write pen_release in a way that is guaranteed to be visible to all + * observers, irrespective of whether they're taking part in coherency + * or not. This is necessary for the hotplug code to work reliably. + */ +static void write_pen_release(int val) { - return scu_get_core_count(__io_address(UX500_SCU_BASE)); + pen_release = val; + smp_wmb(); + __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); } static DEFINE_SPINLOCK(boot_lock); void __cpuinit platform_secondary_init(unsigned int cpu) { - trace_hardirqs_off(); - /* * if any interrupts are already enabled for the primary * core (e.g. timer irq), then they will not have been enabled * for us: do so */ - gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE)); + gic_secondary_init(0); /* * let the primary processor know we're out of the * pen, then head off into the C entry point */ - pen_release = -1; + write_pen_release(-1); /* * Synchronise with the boot thread. @@@ -79,9 -74,11 +79,9 @@@ int __cpuinit boot_secondary(unsigned i * the holding pen - release it, then wait for it to flag * that it has been released by resetting pen_release. */ - pen_release = cpu; - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release) + 1); + write_pen_release(cpu); - smp_cross_call(cpumask_of(cpu)); + smp_cross_call(cpumask_of(cpu), 1); timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { @@@ -100,6 -97,9 +100,6 @@@ static void __init wakeup_secondary(void) { - /* nobody is to be released from the pen yet */ - pen_release = -1; - /* * write the address of secondary startup into the backup ram register * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the @@@ -126,26 -126,40 +126,26 @@@ */ void __init smp_init_cpus(void) { - unsigned int i, ncores = get_core_count(); + unsigned int i, ncores; - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); -} - -void __init smp_prepare_cpus(unsigned int max_cpus) -{ - unsigned int ncores = get_core_count(); - unsigned int cpu = smp_processor_id(); - int i; + ncores = scu_get_core_count(__io_address(UX500_SCU_BASE)); /* sanity check */ - if (ncores == 0) { - printk(KERN_ERR - "U8500: strange CM count of 0? Default to 1\n"); - ncores = 1; - } - - if (ncores > num_possible_cpus()) { + if (ncores > NR_CPUS) { printk(KERN_WARNING "U8500: no. of cores (%d) greater than configured " "maximum of %d - clipping\n", - ncores, num_possible_cpus()); - ncores = num_possible_cpus(); + ncores, NR_CPUS); + ncores = NR_CPUS; } - smp_store_cpu_info(cpu); + for (i = 0; i < ncores; i++) + set_cpu_possible(i, true); +} - /* - * are we trying to boot more cores than exist? - */ - if (max_cpus > ncores) - max_cpus = ncores; +void __init platform_smp_prepare_cpus(unsigned int max_cpus) +{ + int i; /* * Initialise the present map, which describes the set of CPUs @@@ -154,6 -168,13 +154,6 @@@ for (i = 0; i < max_cpus; i++) set_cpu_present(i, true); - if (max_cpus > 1) { - /* - * Enable the local timer or broadcast device for the - * boot CPU, but only if we have more than one CPU. - */ - percpu_timer_setup(); - scu_enable(__io_address(UX500_SCU_BASE)); - wakeup_secondary(); - } + scu_enable(__io_address(UX500_SCU_BASE)); + wakeup_secondary(); } diff --combined arch/arm/mm/Kconfig index 8493ed04797a,a099efed0e63..49db8b3e4a49 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@@ -382,6 -382,12 +382,12 @@@ config CPU_FEROCEON_OLD_I for which the CPU ID is equal to the ARM926 ID. Relevant for Feroceon-1850 and early Feroceon-2850. + # Marvell PJ4 + config CPU_PJ4 + bool + select CPU_V7 + select ARM_THUMBEE + # ARMv6 config CPU_V6 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE @@@ -599,14 -605,6 +605,14 @@@ config CPU_CP15_MP help Processor has the CP15 register, which has MPU related registers. +config CPU_USE_DOMAINS + bool + depends on MMU + default y if !CPU_32v6K + help + This option enables or disables the use of domain switching + via the set_fs() function. + # # CPU supports 36-bit I/O # @@@ -636,33 -634,6 +642,33 @@@ config ARM_THUMBE Say Y here if you have a CPU with the ThumbEE extension and code to make use of it. Say N for code that can run on CPUs without ThumbEE. +config SWP_EMULATE + bool "Emulate SWP/SWPB instructions" + depends on CPU_V7 + select HAVE_PROC_CPU if PROC_FS + default y if SMP + help + ARMv6 architecture deprecates use of the SWP/SWPB instructions. + ARMv7 multiprocessing extensions introduce the ability to disable + these instructions, triggering an undefined instruction exception + when executed. Say Y here to enable software emulation of these + instructions for userspace (not kernel) using LDREX/STREX. + Also creates /proc/cpu/swp_emulation for statistics. + + In some older versions of glibc [<=2.8] SWP is used during futex + trylock() operations with the assumption that the code will not + be preempted. This invalid assumption may be more likely to fail + with SWP emulation enabled, leading to deadlock of the user + application. + + NOTE: when accessing uncached shared regions, LDREX/STREX rely + on an external transaction monitoring block called a global + monitor to maintain update atomicity. If your system does not + implement a global monitor, this option can cause programs that + perform SWP operations to uncached memory to deadlock. + + If unsure, say Y. + config CPU_BIG_ENDIAN bool "Build big-endian kernel" depends on ARCH_SUPPORTS_BIG_ENDIAN @@@ -824,7 -795,7 +830,7 @@@ config CACHE_PL31 config CACHE_TAUROS2 bool "Enable the Tauros2 L2 cache controller" - depends on (ARCH_DOVE || ARCH_MMP) + depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4) default y select OUTER_CACHE help diff --combined drivers/pcmcia/Makefile index a565300a19c8,9a44a90dcf7a..29935ea921df --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@@ -50,9 -50,8 +50,9 @@@ sa1111_cs-$(CONFIG_SA1100_JORNADA720) sa1100_cs-y += sa1100_generic.o sa1100_cs-$(CONFIG_SA1100_ASSABET) += sa1100_assabet.o sa1100_cs-$(CONFIG_SA1100_CERF) += sa1100_cerf.o -sa1100_cs-$(CONFIG_SA1100_COLLIE) += pxa2xx_sharpsl.o +sa1100_cs-$(CONFIG_SA1100_COLLIE) += pxa2xx_sharpsl.o sa1100_cs-$(CONFIG_SA1100_H3600) += sa1100_h3600.o +sa1100_cs-$(CONFIG_SA1100_NANOENGINE) += sa1100_nanoengine.o sa1100_cs-$(CONFIG_SA1100_SHANNON) += sa1100_shannon.o sa1100_cs-$(CONFIG_SA1100_SIMPAD) += sa1100_simpad.o @@@ -71,6 -70,8 +71,8 @@@ pxa2xx-obj-$(CONFIG_MACH_E740) += pxa pxa2xx-obj-$(CONFIG_MACH_STARGATE2) += pxa2xx_stargate2.o pxa2xx-obj-$(CONFIG_MACH_VPAC270) += pxa2xx_vpac270.o pxa2xx-obj-$(CONFIG_MACH_BALLOON3) += pxa2xx_balloon3.o + pxa2xx-obj-$(CONFIG_MACH_COLIBRI) += pxa2xx_colibri.o + pxa2xx-obj-$(CONFIG_MACH_COLIBRI320) += pxa2xx_colibri.o obj-$(CONFIG_PCMCIA_PXA2XX) += pxa2xx_base.o $(pxa2xx-obj-y)