From: H Hartley Sweeten Date: Fri, 1 May 2015 21:58:36 +0000 (-0700) Subject: staging: comedi: ni_stc.h: tidy up NI_M_CLK_FOUT2_REG bits X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=40aafd79a8b82ba506e28009cfa7c46bba813ce8;p=linux-beck.git staging: comedi: ni_stc.h: tidy up NI_M_CLK_FOUT2_REG bits Rename the CamelCase and convert the enum into defines. Use the BIT() macro to define the bits. Convert the inline function MSeries_PLL_In_Source_Select_RTSI_Bits() to a macro. The caller always passes valid values for 'RTIS_channel' so the sanity checking can safely be removed. Tidy up ni_mseries_set_pll_master_clock() to remove the unnecessary extra indent level for the code that sets a RTSI channel for the PLL source. Signed-off-by: H Hartley Sweeten Reviewed-by: Ian Abbott Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/staging/comedi/drivers/ni_mio_common.c b/drivers/staging/comedi/drivers/ni_mio_common.c index 0cd5fc24759b..9fef0e938626 100644 --- a/drivers/staging/comedi/drivers/ni_mio_common.c +++ b/drivers/staging/comedi/drivers/ni_mio_common.c @@ -4684,6 +4684,7 @@ static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, unsigned pll_control_bits; unsigned freq_divider; unsigned freq_multiplier; + unsigned rtsi; unsigned i; int retval; @@ -4701,37 +4702,27 @@ static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, RTSI_Trig_Direction_Register); pll_control_bits = MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits; - devpriv->clock_and_fout2 |= - MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit; - devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask; + devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL | + NI_M_CLK_FOUT2_TIMEBASE3_PLL; + devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK; switch (source) { case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK: - devpriv->clock_and_fout2 |= - MSeries_PLL_In_Source_Select_Star_Trigger_Bits; + devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR; break; case NI_MIO_PLL_PXI10_CLOCK: /* pxi clock is 10MHz */ - devpriv->clock_and_fout2 |= - MSeries_PLL_In_Source_Select_PXI_Clock10; + devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10; break; default: - { - unsigned rtsi_channel; - static const unsigned max_rtsi_channel = 7; - - for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel; - ++rtsi_channel) { - if (source == - NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) { - devpriv->clock_and_fout2 |= - MSeries_PLL_In_Source_Select_RTSI_Bits - (rtsi_channel); - break; - } + for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) { + if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) { + devpriv->clock_and_fout2 |= + NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi); + break; } - if (rtsi_channel > max_rtsi_channel) - return -EINVAL; } + if (rtsi > NI_M_MAX_RTSI_CHAN) + return -EINVAL; break; } retval = ni_mseries_get_pll_parameters(period_ns, @@ -4778,8 +4769,8 @@ static int ni_set_master_clock(struct comedi_device *dev, devpriv->clock_ns = TIMEBASE_1_NS; if (devpriv->is_m_series) { devpriv->clock_and_fout2 &= - ~(MSeries_Timebase1_Select_Bit | - MSeries_Timebase3_Select_Bit); + ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL | + NI_M_CLK_FOUT2_TIMEBASE3_PLL); ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG); ni_writew(dev, 0, NI_M_PLL_CTRL_REG); @@ -4972,8 +4963,13 @@ static void ni_rtsi_init(struct comedi_device *dev) /* Initialises the RTSI bus signal switch to a default state */ + /* + * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears + * to have no effect, at least on pxi-6281, which always uses + * 20MHz rtsi clock frequency + */ + devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ; /* Set clock mode to internal */ - devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit; if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n"); /* default internal lines routing to RTSI bus lines */ diff --git a/drivers/staging/comedi/drivers/ni_stc.h b/drivers/staging/comedi/drivers/ni_stc.h index fb23372d597d..33adb63e1634 100644 --- a/drivers/staging/comedi/drivers/ni_stc.h +++ b/drivers/staging/comedi/drivers/ni_stc.h @@ -968,6 +968,17 @@ static const struct comedi_lrange range_ni_E_ao_ext; #define NI_M_AO_CFG_BANK_REG(x) (0x0c3 + ((x) * 4)) #define NI_M_RTSI_SHARED_MUX_REG 0x1a2 #define NI_M_CLK_FOUT2_REG 0x1c4 +#define NI_M_CLK_FOUT2_RTSI_10MHZ BIT(7) +#define NI_M_CLK_FOUT2_TIMEBASE3_PLL BIT(6) +#define NI_M_CLK_FOUT2_TIMEBASE1_PLL BIT(5) +#define NI_M_CLK_FOUT2_PLL_SRC(x) (((x) & 0x1f) << 0) +#define NI_M_CLK_FOUT2_PLL_SRC_MASK NI_M_CLK_FOUT2_PLL_SRC(0x1f) +#define NI_M_MAX_RTSI_CHAN 7 +#define NI_M_CLK_FOUT2_PLL_SRC_RTSI(x) (((x) == NI_M_MAX_RTSI_CHAN) \ + ? NI_M_CLK_FOUT2_PLL_SRC(0x1b) \ + : NI_M_CLK_FOUT2_PLL_SRC(0xb + (x))) +#define NI_M_CLK_FOUT2_PLL_SRC_STAR NI_M_CLK_FOUT2_PLL_SRC(0x14) +#define NI_M_CLK_FOUT2_PLL_SRC_PXI10 NI_M_CLK_FOUT2_PLL_SRC(0x1d) #define NI_M_PLL_CTRL_REG 0x1c6 #define NI_M_PLL_STATUS_REG 0x1c8 #define NI_M_PFI_OUT_SEL_REG(x) (0x1d0 + ((x) * 2)) @@ -986,33 +997,6 @@ static const struct comedi_lrange range_ni_E_ao_ext; #define NI_M_STATIC_AI_CTRL_REG(x) ((x) ? (0x260 + (x)) : 0x064) #define NI_M_AO_REF_ATTENUATION_REG(x) (0x264 + (x)) -enum MSeries_Clock_and_Fout2_Bits { - MSeries_PLL_In_Source_Select_RTSI0_Bits = 0xb, - MSeries_PLL_In_Source_Select_Star_Trigger_Bits = 0x14, - MSeries_PLL_In_Source_Select_RTSI7_Bits = 0x1b, - MSeries_PLL_In_Source_Select_PXI_Clock10 = 0x1d, - MSeries_PLL_In_Source_Select_Mask = 0x1f, - MSeries_Timebase1_Select_Bit = 0x20, /* use PLL for timebase 1 */ - MSeries_Timebase3_Select_Bit = 0x40, /* use PLL for timebase 3 */ - /* use 10MHz instead of 20MHz for RTSI clock frequency. Appears - to have no effect, at least on pxi-6281, which always uses - 20MHz rtsi clock frequency */ - MSeries_RTSI_10MHz_Bit = 0x80 -}; -static inline unsigned MSeries_PLL_In_Source_Select_RTSI_Bits(unsigned - RTSI_channel) -{ - if (RTSI_channel > 7) { - pr_err("%s: bug, invalid RTSI_channel=%i\n", __func__, - RTSI_channel); - return 0; - } - if (RTSI_channel == 7) - return MSeries_PLL_In_Source_Select_RTSI7_Bits; - else - return MSeries_PLL_In_Source_Select_RTSI0_Bits + RTSI_channel; -} - enum MSeries_PLL_Control_Bits { MSeries_PLL_Enable_Bit = 0x1000, MSeries_PLL_VCO_Mode_200_325MHz_Bits = 0x0,