From: Maxime Ripard Date: Tue, 1 Jul 2014 09:33:14 +0000 (+0200) Subject: ARM: at91: PIT: Follow the general coding rules X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=52c3ffb018f4af038039f783d932ba5c99e4a87b;p=linux-beck.git ARM: at91: PIT: Follow the general coding rules Replace all masks and bits definitions by matching calls to BIT and GENMASK. While we're at it, also fix a few style issues. Signed-off-by: Maxime Ripard Acked-by: Boris BREZILLON Acked-by: Alexandre Belloni Acked-by: Daniel Lezcano Signed-off-by: Nicolas Ferre --- diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c index 0a9e2fc8f796..fd3170b65fbb 100644 --- a/arch/arm/mach-at91/at91sam926x_time.c +++ b/arch/arm/mach-at91/at91sam926x_time.c @@ -9,11 +9,12 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ + +#include +#include #include #include #include -#include -#include #include #include #include @@ -22,17 +23,17 @@ #include #define AT91_PIT_MR 0x00 /* Mode Register */ -#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ -#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ -#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ +#define AT91_PIT_PITIEN BIT(25) /* Timer Interrupt Enable */ +#define AT91_PIT_PITEN BIT(24) /* Timer Enabled */ +#define AT91_PIT_PIV GENMASK(19, 0) /* Periodic Interval Value */ #define AT91_PIT_SR 0x04 /* Status Register */ -#define AT91_PIT_PITS (1 << 0) /* Timer Status */ +#define AT91_PIT_PITS BIT(0) /* Timer Status */ #define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */ #define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */ -#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ -#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ +#define AT91_PIT_PICNT GENMASK(31, 20) /* Interval Counter */ +#define AT91_PIT_CPIV GENMASK(19, 0) /* Inverval Value */ #define PIT_CPIV(x) ((x) & AT91_PIT_CPIV) #define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)