From: Andrey Smirnov Date: Wed, 3 Aug 2016 19:33:34 +0000 (+0100) Subject: ARM: 8593/1: cache-l2x0.c: Do not clear bit 23 in prefetch control register X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=55604b7ab1b5b8f560721e69b1ac059bd8d2078e;p=linux-beck.git ARM: 8593/1: cache-l2x0.c: Do not clear bit 23 in prefetch control register As per L2C-310 TRM[1]: "... You can control this feature using bits 30,27 and 23 of the Prefetch Control Register. Bit 23 and 27 are only used if you set bit 30 HIGH..." which means there is no need to clear bit 23 if bit 30 is being cleared. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246e/CJAJACBJ.html Acked-by: Arnd Bergmann Signed-off-by: Andrey Smirnov Signed-off-by: Russell King --- diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 7e624872bd6f..ca5595fa072a 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -709,11 +709,8 @@ static void __init l2c310_fixup(void __iomem *base, u32 cache_id, if (revision >= L310_CACHE_ID_RTL_R3P0 && revision < L310_CACHE_ID_RTL_R3P2) { u32 val = l2x0_saved_regs.prefetch_ctrl; - /* I don't think bit23 is required here... but iMX6 does so */ - if (val & (L310_PREFETCH_CTRL_DBL_LINEFILL | - L310_PREFETCH_CTRL_DBL_LINEFILL_INCR)) { - val &= ~(L310_PREFETCH_CTRL_DBL_LINEFILL | - L310_PREFETCH_CTRL_DBL_LINEFILL_INCR); + if (val & L310_PREFETCH_CTRL_DBL_LINEFILL) { + val &= ~L310_PREFETCH_CTRL_DBL_LINEFILL; l2x0_saved_regs.prefetch_ctrl = val; errata[n++] = "752271"; }