From: Bill Huang <bilhuang@nvidia.com>
Date: Thu, 18 Jun 2015 21:28:22 +0000 (-0400)
Subject: clk: tegra: pll: Change misc_reg count from 3 to 6
X-Git-Tag: v4.5-rc1~82^2~1^2~17
X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=56fd27b31f1a216623f285bb77b4bcb6129e84c2;p=karo-tx-linux.git

clk: tegra: pll: Change misc_reg count from 3 to 6

New SoC's may have more than 3 MISC registers, so bump up the array size
and use a #define to be more informative about the value.

Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---

diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index ced19e7c68d2..488ee677e15b 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -156,6 +156,8 @@ struct div_nmp {
 	u8		override_divp_shift;
 };
 
+#define MAX_PLL_MISC_REG_COUNT	6
+
 /**
  * struct tegra_clk_pll_params - PLL parameters
  *
@@ -225,7 +227,7 @@ struct tegra_clk_pll_params {
 	u32		iddq_bit_idx;
 	u32		aux_reg;
 	u32		dyn_ramp_reg;
-	u32		ext_misc_reg[3];
+	u32		ext_misc_reg[MAX_PLL_MISC_REG_COUNT];
 	u32		pmc_divnm_reg;
 	u32		pmc_divp_reg;
 	u32		flags;