From: Shawn Lin Date: Tue, 11 Apr 2017 21:27:02 +0000 (-0500) Subject: PCI: rockchip: Set PCI_EXP_LNKSTA_SLC in the Root Port X-Git-Tag: v4.12-rc1~65^2~13^2~3 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=64d6ea602ce619633a6e0af979e2c73738f6aeba;p=karo-tx-linux.git PCI: rockchip: Set PCI_EXP_LNKSTA_SLC in the Root Port All platforms using Rockchip use a common clock for the Root Port and the slot connected to it. Indicate this by setting the Slot Clock Configuration (PCI_EXP_LNKSTA_SLC) bit in the Root Port's Link Status. Per the Implementation Note in the spec (PCIe r3.1, sec 7.8.7), if the downstream component also sets PCI_EXP_LNKSTA_SLC, software may set the Common Clock Configuration (PCI_EXP_LNKCTL_CCC) bits on both ends of the Link. This is done by pcie_aspm_configure_common_clock(). Signed-off-by: Shawn Lin Cc: Brian Norris Cc: jeffy.chen --- diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index a7467212ea18..94feb7dfd8f4 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -598,7 +598,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) /* Set RC's clock architecture as common clock */ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); - status |= PCI_EXP_LNKCTL_CCC; + status |= PCI_EXP_LNKSTA_SLC << 16; rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); /* Set RC's RCB to 128 */