From: Arend van Spriel Date: Tue, 3 May 2011 09:35:39 +0000 (+0200) Subject: staging: brcm80211: fix checkpatch warnings in si_pmu_spuravoid_pllupdate X-Git-Tag: v3.0-rc1~336^2~554 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=683d06921d7a7e75e310fd2d579ffdc8c6e88e27;p=karo-tx-linux.git staging: brcm80211: fix checkpatch warnings in si_pmu_spuravoid_pllupdate patch "remove dependency between aiutils and siutils sources" resulted in several checkpatch warnings and errors. This patch fixes those in function si_pmu_spuravoid_pllupdate(). Cc: devel@linuxdriverproject.org Cc: linux-wireless@vger.kernel.org Cc: Brett Rudley Cc: Henry Ptasinski Cc: Roland Vossen Signed-off-by: Arend van Spriel Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_pmu.c b/drivers/staging/brcm80211/brcmsmac/wlc_pmu.c index 4bb14c5226da..603172addca9 100644 --- a/drivers/staging/brcm80211/brcmsmac/wlc_pmu.c +++ b/drivers/staging/brcm80211/brcmsmac/wlc_pmu.c @@ -683,7 +683,10 @@ si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, u8 spuravoid) case BCM43236_CHIP_ID: case BCM43238_CHIP_ID: - /* BCM5357 needs to touch PLL1_PLLCTL[02], so offset PLL0_PLLCTL[02] by 6 */ + /* + * BCM5357 needs to touch PLL1_PLLCTL[02], + * so offset PLL0_PLLCTL[02] by 6 + */ phypll_offset = (sih->chip == BCM5357_CHIP_ID) ? 6 : 0; /* RMW only the P1 divider */ @@ -821,10 +824,12 @@ si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, u8 spuravoid) W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); W_REG(&cc->pllcontrol_data, 0x88888854); - if (spuravoid == 1) { /* spur_avoid ON, enable 41/82/164Mhz clock mode */ + if (spuravoid == 1) { + /* spur_avoid ON, so enable 41/82/164Mhz clock mode */ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); W_REG(&cc->pllcontrol_data, 0x05201828); - } else { /* enable 40/80/160Mhz clock mode */ + } else { + /* enable 40/80/160Mhz clock mode */ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); W_REG(&cc->pllcontrol_data, 0x05001828); } @@ -847,11 +852,10 @@ si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, u8 spuravoid) W_REG(&cc->pllcontrol_data, 0x88888825); W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); - if (spuravoid == 1) { + if (spuravoid == 1) W_REG(&cc->pllcontrol_data, 0x00EC4EC4); - } else { + else W_REG(&cc->pllcontrol_data, 0x00762762); - } tmp = PCTL_PLL_PLLCTL_UPD; break;