From: Lothar Waßmann Date: Fri, 24 Oct 2014 10:31:24 +0000 (+0200) Subject: Merge branch 'tx53-1232' X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=684ac69a5ada4e004178ace7c6cbeb9e20d8ec4b;hp=53890440f8ee1e79d9566bf920eac7334645c2e4;p=karo-tx-uboot.git Merge branch 'tx53-1232' --- diff --git a/board/karo/tx53/lowlevel_init.S b/board/karo/tx53/lowlevel_init.S index b530fdb91d..566667cd8e 100644 --- a/board/karo/tx53/lowlevel_init.S +++ b/board/karo/tx53/lowlevel_init.S @@ -8,13 +8,7 @@ #define LED_MUX_MODE 0x11 #define SDRAM_CLK CONFIG_SYS_SDRAM_CLK - -#ifdef PHYS_SDRAM_2_SIZE -#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) -#else -#define SDRAM_SIZE PHYS_SDRAM_1_SIZE -#endif - +#define SDRAM_SIZE (CONFIG_SYS_SDRAM_SIZE / SZ_1M) #define REG_CCGR0 0x68 #define REG_CCGR1 0x6c @@ -111,6 +105,7 @@ dcd_end: #define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK) #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000) #define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10) +#define NS_TO_CK100(ns) DIV_ROUND_UP(NS_TO_CK(ns), 100) .macro CK_VAL, name, clks, offs, max .iflt \clks - \offs @@ -150,11 +145,7 @@ dcd_end: #define ESDOR_CLK_PERIOD_ns (1000000000 / CKIL_FREQ_Hz / 2) /* base clock for ESDOR values */ /* DDR3 SDRAM */ -#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE -#define BANK_ADDR_BITS 2 -#else -#define BANK_ADDR_BITS 1 -#endif +#define BANK_ADDR_BITS CONFIG_NR_DRAM_BANKS #define SDRAM_BURST_LENGTH 8 #define RALAT 5 #define WALAT 0 @@ -162,7 +153,6 @@ dcd_end: #define ADDR_MIRROR 0 #define DDR_TYPE ESDMISC_DDR_TYPE_DDR3 -/* 512/1024MiB SDRAM: NT5CB128M16FP-DII */ #if SDRAM_CLK > 666 && SDRAM_CLK <= 800 #define CL_VAL 11 #define CWL_VAL 8 @@ -182,6 +172,8 @@ dcd_end: #error SDRAM clock out of range: 303 .. 800 #endif +#if SDRAM_SIZE < 2048 +/* 512/1024MiB SDRAM: NT5CB128M16FP-DII */ /* ESDCFG0 0x0c */ NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */ CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ @@ -208,13 +200,42 @@ CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) */ /* ESDOR 0x30 */ CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ +#else +/* 4096MiB SDRAM: IM4G16D3EABG-125I */ +/* ESDCFG0 0x0c */ +NS_VAL tRFC, 260, 1, 255 /* clks - 1 (0..255) */ +CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ +CK_MAX tXP, NS_TO_CK(6), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */ +CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */ +NS_VAL tFAW, 30, 1, 31 /* clks - 1 (0..31) */ +CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */ + +/* ESDCFG1 0x10 */ +CK_VAL tRCD, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */ +CK_VAL tRP, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */ +CK_VAL tRC, NS_TO_CK100(4875), 1, 31 /* clks - 1 (0..31) */ /* 48.75 */ +CK_VAL tRAS, NS_TO_CK(35), 1, 31 /* clks - 1 (0..31) */ /* 35 */ +CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */ +NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */ + +/* ESDCFG2 0x14 */ +CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ +CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ +CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ +CK_MAX tRRD, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ + +/* ESDOR 0x30 */ +CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ +#endif + #define tSDE_RST (DIV_ROUND_UP(200000, ESDOR_CLK_PERIOD_ns) + 1) /* Add an extra (or two?) ESDOR_CLK_PERIOD_ns according to * erroneous Erratum Engcm12377 */ #define tRST_CKE (DIV_ROUND_UP(500000 + 2 * ESDOR_CLK_PERIOD_ns, ESDOR_CLK_PERIOD_ns) + 1) - /* ESDOTC 0x08 */ CK_VAL tAOFPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */ CK_VAL tAONPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */ diff --git a/board/karo/tx53/tx53.c b/board/karo/tx53/tx53.c index df666fcfa1..06a9a4b5a2 100644 --- a/board/karo/tx53/tx53.c +++ b/board/karo/tx53/tx53.c @@ -377,7 +377,7 @@ int adjust_core_voltage(u32 freq) u8 val = mV_to_regval(vout_to_vref(mV * 10, 3)); u8 v; - printf("regval[%umV]=%02x\n", mV, val); + debug("regval[%umV]=%02x\n", mV, val); ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1, &v, 1); @@ -386,7 +386,7 @@ int adjust_core_voltage(u32 freq) __func__, LTC3589_B1DTV1, ret); return ret; } - printf("Changing reg %02x from %02x to %02x\n", + debug("Changing reg %02x from %02x to %02x\n", LTC3589_B1DTV1, v, (v & ~0x1f) | mV_to_regval(vout_to_vref(mV * 10, 3))); v &= ~0x1f; @@ -502,9 +502,13 @@ int dram_init(void) { int ret; - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); + /* + * U-Boot doesn't support RAM banks with intervening holes, + * so let U-Boot only know about the first bank for its + * internal data structures. The size reported to Linux is + * determined from the individual bank sizes. + */ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, SZ_1G); ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK); @@ -521,14 +525,24 @@ int dram_init(void) void dram_init_banksize(void) { + long total_size = gd->ram_size; + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); + gd->bd->bi_dram[0].size = gd->ram_size; + #if CONFIG_NR_DRAM_BANKS > 1 - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, - PHYS_SDRAM_2_SIZE); + gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, SZ_1G); + + if (gd->bd->bi_dram[1].size) { + debug("Found %luMiB SDRAM in bank 2\n", + gd->bd->bi_dram[1].size / SZ_1M); + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + total_size += gd->bd->bi_dram[1].size; + } #endif + if (total_size != CONFIG_SYS_SDRAM_SIZE) + printf("WARNING: SDRAM size mismatch: %uMiB configured; %luMiB detected\n", + CONFIG_SYS_SDRAM_SIZE / SZ_1M, total_size / SZ_1M); } #ifdef CONFIG_CMD_MMC @@ -1352,10 +1366,16 @@ exit: int checkboard(void) { tx53_print_cpuinfo(); - - printf("Board: Ka-Ro TX53-x%d3%s\n", - is_lvds(), TX53_MOD_SUFFIX); - +#if CONFIG_SYS_SDRAM_SIZE < SZ_1G + printf("Board: Ka-Ro TX53-8%d3%c\n", + is_lvds(), '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G); +#elif CONFIG_SYS_SDRAM_SIZE < SZ_2G + printf("Board: Ka-Ro TX53-1%d3%c\n", + is_lvds() + 2, '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G); +#else + printf("Board: Ka-Ro TX53-123%c\n", + '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G); +#endif return 0; } diff --git a/boards.cfg b/boards.cfg index c6ae7856c0..6e3c5d4f69 100644 --- a/boards.cfg +++ b/boards.cfg @@ -280,6 +280,7 @@ tx51-8xx1_2 arm armv7 tx51 karo m tx53-x030 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=1 tx53-x130 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=1,SYS_LVDS_IF tx53-x131 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=2,SYS_LVDS_IF +tx53-1232 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=2,SYS_SDRAM_SIZE=SZ_2G tx6q-1010 arm armv7 tx6 karo mx6 tx6:MX6Q tx6q-1010_mfg arm armv7 tx6 karo mx6 tx6:MX6Q,MFG tx6q-1010_noenv arm armv7 tx6 karo mx6 tx6:MX6Q,ENV_IS_NOWHERE diff --git a/include/configs/tx53.h b/include/configs/tx53.h index 33292bb8db..2ffb5b1263 100644 --- a/include/configs/tx53.h +++ b/include/configs/tx53.h @@ -43,14 +43,15 @@ /* * Memory configuration options */ +#ifndef CONFIG_SYS_SDRAM_SIZE +#define CONFIG_SYS_SDRAM_SIZE (SZ_512M * CONFIG_NR_DRAM_BANKS) +#endif + #define PHYS_SDRAM_1 0x70000000 /* Base address of bank 1 */ -#define PHYS_SDRAM_1_SIZE SZ_512M +#define PHYS_SDRAM_1_SIZE (CONFIG_SYS_SDRAM_SIZE / CONFIG_NR_DRAM_BANKS) #if CONFIG_NR_DRAM_BANKS > 1 #define PHYS_SDRAM_2 0xb0000000 /* Base address of bank 2 */ -#define PHYS_SDRAM_2_SIZE SZ_512M -#define TX53_MOD_SUFFIX "1" -#else -#define TX53_MOD_SUFFIX "0" +#define PHYS_SDRAM_2_SIZE PHYS_SDRAM_1_SIZE #endif #define CONFIG_STACKSIZE SZ_128K #define CONFIG_SYS_MALLOC_LEN SZ_8M @@ -139,7 +140,7 @@ "default_bootargs=set bootargs " CONFIG_BOOTARGS \ " ${append_bootargs}\0" \ "fdtaddr=71000000\0" \ - "fdtsave=fdt resize;nand erase.part dtb" \ + "fdtsave=fdt resize;nand erase.part dtb" \ ";nand write ${fdtaddr} dtb ${fdtsize}\0" \ "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \