From: Kevin Hilman <khilman@deeprootsystems.com>
Date: Fri, 1 Oct 2010 20:24:10 +0000 (-0700)
Subject: manual merge for pm-hwmod-uart due to conflicts
X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=69758ab7a1e2de5636a2188d5357dd03140bf1d8;p=linux-beck.git

manual merge for pm-hwmod-uart due to conflicts
---

69758ab7a1e2de5636a2188d5357dd03140bf1d8
diff --cc arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 66678d98ad96,ba145f7d5896..adf6e3632a2b
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@@ -167,74 -226,144 +228,206 @@@ static struct omap_hwmod omap2420_iva_h
  	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
  };
  
 +/* l4_wkup -> wd_timer2 */
 +static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
 +	{
 +		.pa_start	= 0x48022000,
 +		.pa_end		= 0x4802207f,
 +		.flags		= ADDR_TYPE_RT
 +	},
 +};
 +
 +static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
 +	.master		= &omap2420_l4_wkup_hwmod,
 +	.slave		= &omap2420_wd_timer2_hwmod,
 +	.clk		= "mpu_wdt_ick",
 +	.addr		= omap2420_wd_timer2_addrs,
 +	.addr_cnt	= ARRAY_SIZE(omap2420_wd_timer2_addrs),
 +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
 +/*
 + * 'wd_timer' class
 + * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 + * overflow condition
 + */
 +
 +static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
 +	.rev_offs	= 0x0000,
 +	.sysc_offs	= 0x0010,
 +	.syss_offs	= 0x0014,
 +	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
 +			   SYSC_HAS_AUTOIDLE),
 +	.sysc_fields    = &omap_hwmod_sysc_type1,
 +};
 +
 +static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
 +	.name = "wd_timer",
 +	.sysc = &omap2420_wd_timer_sysc,
 +};
 +
 +/* wd_timer2 */
 +static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
 +	&omap2420_l4_wkup__wd_timer2,
 +};
 +
 +static struct omap_hwmod omap2420_wd_timer2_hwmod = {
 +	.name		= "wd_timer2",
 +	.class		= &omap2420_wd_timer_hwmod_class,
 +	.main_clk	= "mpu_wdt_fck",
 +	.prcm		= {
 +		.omap2 = {
 +			.prcm_reg_id = 1,
 +			.module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 +			.module_offs = WKUP_MOD,
 +			.idlest_reg_id = 1,
 +			.idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 +		},
 +	},
 +	.slaves		= omap2420_wd_timer2_slaves,
 +	.slaves_cnt	= ARRAY_SIZE(omap2420_wd_timer2_slaves),
 +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 +};
 +
+ /* UART */
+ 
+ static struct omap_hwmod_class_sysconfig uart_sysc = {
+ 	.rev_offs	= 0x50,
+ 	.sysc_offs	= 0x54,
+ 	.syss_offs	= 0x58,
+ 	.sysc_flags	= (SYSC_HAS_SIDLEMODE |
+ 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ 			   SYSC_HAS_AUTOIDLE),
+ 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ 	.sysc_fields    = &omap_hwmod_sysc_type1,
+ };
+ 
+ static struct omap_hwmod_class uart_class = {
+ 	.name = "uart",
+ 	.sysc = &uart_sysc,
+ };
+ 
+ /* UART1 */
+ 
+ static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
+ 	{ .irq = INT_24XX_UART1_IRQ, },
+ };
+ 
+ static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+ 	{ .name = "rx",	.dma_req = OMAP24XX_DMA_UART1_RX, },
+ 	{ .name = "tx",	.dma_req = OMAP24XX_DMA_UART1_TX, },
+ };
+ 
+ static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
+ 	&omap2_l4_core__uart1,
+ };
+ 
+ static struct omap_hwmod omap2420_uart1_hwmod = {
+ 	.name		= "uart1",
+ 	.mpu_irqs	= uart1_mpu_irqs,
+ 	.mpu_irqs_cnt	= ARRAY_SIZE(uart1_mpu_irqs),
+ 	.sdma_reqs	= uart1_sdma_reqs,
+ 	.sdma_reqs_cnt	= ARRAY_SIZE(uart1_sdma_reqs),
+ 	.main_clk	= "uart1_fck",
+ 	.prcm		= {
+ 		.omap2 = {
+ 			.module_offs = CORE_MOD,
+ 			.prcm_reg_id = 1,
+ 			.module_bit = OMAP24XX_EN_UART1_SHIFT,
+ 			.idlest_reg_id = 1,
+ 			.idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
+ 		},
+ 	},
+ 	.slaves		= omap2420_uart1_slaves,
+ 	.slaves_cnt	= ARRAY_SIZE(omap2420_uart1_slaves),
+ 	.class		= &uart_class,
+ 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+ };
+ 
+ /* UART2 */
+ 
+ static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
+ 	{ .irq = INT_24XX_UART2_IRQ, },
+ };
+ 
+ static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+ 	{ .name = "rx",	.dma_req = OMAP24XX_DMA_UART2_RX, },
+ 	{ .name = "tx",	.dma_req = OMAP24XX_DMA_UART2_TX, },
+ };
+ 
+ static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
+ 	&omap2_l4_core__uart2,
+ };
+ 
+ static struct omap_hwmod omap2420_uart2_hwmod = {
+ 	.name		= "uart2",
+ 	.mpu_irqs	= uart2_mpu_irqs,
+ 	.mpu_irqs_cnt	= ARRAY_SIZE(uart2_mpu_irqs),
+ 	.sdma_reqs	= uart2_sdma_reqs,
+ 	.sdma_reqs_cnt	= ARRAY_SIZE(uart2_sdma_reqs),
+ 	.main_clk	= "uart2_fck",
+ 	.prcm		= {
+ 		.omap2 = {
+ 			.module_offs = CORE_MOD,
+ 			.prcm_reg_id = 1,
+ 			.module_bit = OMAP24XX_EN_UART2_SHIFT,
+ 			.idlest_reg_id = 1,
+ 			.idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
+ 		},
+ 	},
+ 	.slaves		= omap2420_uart2_slaves,
+ 	.slaves_cnt	= ARRAY_SIZE(omap2420_uart2_slaves),
+ 	.class		= &uart_class,
+ 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+ };
+ 
+ /* UART3 */
+ 
+ static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
+ 	{ .irq = INT_24XX_UART3_IRQ, },
+ };
+ 
+ static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+ 	{ .name = "rx",	.dma_req = OMAP24XX_DMA_UART3_RX, },
+ 	{ .name = "tx",	.dma_req = OMAP24XX_DMA_UART3_TX, },
+ };
+ 
+ static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
+ 	&omap2_l4_core__uart3,
+ };
+ 
+ static struct omap_hwmod omap2420_uart3_hwmod = {
+ 	.name		= "uart3",
+ 	.mpu_irqs	= uart3_mpu_irqs,
+ 	.mpu_irqs_cnt	= ARRAY_SIZE(uart3_mpu_irqs),
+ 	.sdma_reqs	= uart3_sdma_reqs,
+ 	.sdma_reqs_cnt	= ARRAY_SIZE(uart3_sdma_reqs),
+ 	.main_clk	= "uart3_fck",
+ 	.prcm		= {
+ 		.omap2 = {
+ 			.module_offs = CORE_MOD,
+ 			.prcm_reg_id = 2,
+ 			.module_bit = OMAP24XX_EN_UART3_SHIFT,
+ 			.idlest_reg_id = 2,
+ 			.idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
+ 		},
+ 	},
+ 	.slaves		= omap2420_uart3_slaves,
+ 	.slaves_cnt	= ARRAY_SIZE(omap2420_uart3_slaves),
+ 	.class		= &uart_class,
+ 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+ };
+ 
  static __initdata struct omap_hwmod *omap2420_hwmods[] = {
  	&omap2420_l3_main_hwmod,
  	&omap2420_l4_core_hwmod,
  	&omap2420_l4_wkup_hwmod,
  	&omap2420_mpu_hwmod,
  	&omap2420_iva_hwmod,
 +	&omap2420_wd_timer2_hwmod,
+ 	&omap2420_uart1_hwmod,
+ 	&omap2420_uart2_hwmod,
+ 	&omap2420_uart3_hwmod,
  	NULL,
  };
  
diff --cc arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 7ec927aa23de,d21073d7eb74..12d939e456cf
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@@ -167,74 -226,144 +228,206 @@@ static struct omap_hwmod omap2430_iva_h
  	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
  };
  
 +/* l4_wkup -> wd_timer2 */
 +static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
 +	{
 +		.pa_start	= 0x49016000,
 +		.pa_end		= 0x4901607f,
 +		.flags		= ADDR_TYPE_RT
 +	},
 +};
 +
 +static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
 +	.master		= &omap2430_l4_wkup_hwmod,
 +	.slave		= &omap2430_wd_timer2_hwmod,
 +	.clk		= "mpu_wdt_ick",
 +	.addr		= omap2430_wd_timer2_addrs,
 +	.addr_cnt	= ARRAY_SIZE(omap2430_wd_timer2_addrs),
 +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
 +/*
 + * 'wd_timer' class
 + * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 + * overflow condition
 + */
 +
 +static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
 +	.rev_offs	= 0x0,
 +	.sysc_offs	= 0x0010,
 +	.syss_offs	= 0x0014,
 +	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
 +			   SYSC_HAS_AUTOIDLE),
 +	.sysc_fields    = &omap_hwmod_sysc_type1,
 +};
 +
 +static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
 +	.name = "wd_timer",
 +	.sysc = &omap2430_wd_timer_sysc,
 +};
 +
 +/* wd_timer2 */
 +static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
 +	&omap2430_l4_wkup__wd_timer2,
 +};
 +
 +static struct omap_hwmod omap2430_wd_timer2_hwmod = {
 +	.name		= "wd_timer2",
 +	.class		= &omap2430_wd_timer_hwmod_class,
 +	.main_clk	= "mpu_wdt_fck",
 +	.prcm		= {
 +		.omap2 = {
 +			.prcm_reg_id = 1,
 +			.module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 +			.module_offs = WKUP_MOD,
 +			.idlest_reg_id = 1,
 +			.idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 +		},
 +	},
 +	.slaves		= omap2430_wd_timer2_slaves,
 +	.slaves_cnt	= ARRAY_SIZE(omap2430_wd_timer2_slaves),
 +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 +};
 +
+ /* UART */
+ 
+ static struct omap_hwmod_class_sysconfig uart_sysc = {
+ 	.rev_offs	= 0x50,
+ 	.sysc_offs	= 0x54,
+ 	.syss_offs	= 0x58,
+ 	.sysc_flags	= (SYSC_HAS_SIDLEMODE |
+ 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ 			   SYSC_HAS_AUTOIDLE),
+ 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ 	.sysc_fields    = &omap_hwmod_sysc_type1,
+ };
+ 
+ static struct omap_hwmod_class uart_class = {
+ 	.name = "uart",
+ 	.sysc = &uart_sysc,
+ };
+ 
+ /* UART1 */
+ 
+ static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
+ 	{ .irq = INT_24XX_UART1_IRQ, },
+ };
+ 
+ static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+ 	{ .name = "rx",	.dma_req = OMAP24XX_DMA_UART1_RX, },
+ 	{ .name = "tx",	.dma_req = OMAP24XX_DMA_UART1_TX, },
+ };
+ 
+ static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
+ 	&omap2_l4_core__uart1,
+ };
+ 
+ static struct omap_hwmod omap2430_uart1_hwmod = {
+ 	.name		= "uart1",
+ 	.mpu_irqs	= uart1_mpu_irqs,
+ 	.mpu_irqs_cnt	= ARRAY_SIZE(uart1_mpu_irqs),
+ 	.sdma_reqs	= uart1_sdma_reqs,
+ 	.sdma_reqs_cnt	= ARRAY_SIZE(uart1_sdma_reqs),
+ 	.main_clk	= "uart1_fck",
+ 	.prcm		= {
+ 		.omap2 = {
+ 			.module_offs = CORE_MOD,
+ 			.prcm_reg_id = 1,
+ 			.module_bit = OMAP24XX_EN_UART1_SHIFT,
+ 			.idlest_reg_id = 1,
+ 			.idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
+ 		},
+ 	},
+ 	.slaves		= omap2430_uart1_slaves,
+ 	.slaves_cnt	= ARRAY_SIZE(omap2430_uart1_slaves),
+ 	.class		= &uart_class,
+ 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ };
+ 
+ /* UART2 */
+ 
+ static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
+ 	{ .irq = INT_24XX_UART2_IRQ, },
+ };
+ 
+ static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+ 	{ .name = "rx",	.dma_req = OMAP24XX_DMA_UART2_RX, },
+ 	{ .name = "tx",	.dma_req = OMAP24XX_DMA_UART2_TX, },
+ };
+ 
+ static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
+ 	&omap2_l4_core__uart2,
+ };
+ 
+ static struct omap_hwmod omap2430_uart2_hwmod = {
+ 	.name		= "uart2",
+ 	.mpu_irqs	= uart2_mpu_irqs,
+ 	.mpu_irqs_cnt	= ARRAY_SIZE(uart2_mpu_irqs),
+ 	.sdma_reqs	= uart2_sdma_reqs,
+ 	.sdma_reqs_cnt	= ARRAY_SIZE(uart2_sdma_reqs),
+ 	.main_clk	= "uart2_fck",
+ 	.prcm		= {
+ 		.omap2 = {
+ 			.module_offs = CORE_MOD,
+ 			.prcm_reg_id = 1,
+ 			.module_bit = OMAP24XX_EN_UART2_SHIFT,
+ 			.idlest_reg_id = 1,
+ 			.idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
+ 		},
+ 	},
+ 	.slaves		= omap2430_uart2_slaves,
+ 	.slaves_cnt	= ARRAY_SIZE(omap2430_uart2_slaves),
+ 	.class		= &uart_class,
+ 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ };
+ 
+ /* UART3 */
+ 
+ static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
+ 	{ .irq = INT_24XX_UART3_IRQ, },
+ };
+ 
+ static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+ 	{ .name = "rx",	.dma_req = OMAP24XX_DMA_UART3_RX, },
+ 	{ .name = "tx",	.dma_req = OMAP24XX_DMA_UART3_TX, },
+ };
+ 
+ static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
+ 	&omap2_l4_core__uart3,
+ };
+ 
+ static struct omap_hwmod omap2430_uart3_hwmod = {
+ 	.name		= "uart3",
+ 	.mpu_irqs	= uart3_mpu_irqs,
+ 	.mpu_irqs_cnt	= ARRAY_SIZE(uart3_mpu_irqs),
+ 	.sdma_reqs	= uart3_sdma_reqs,
+ 	.sdma_reqs_cnt	= ARRAY_SIZE(uart3_sdma_reqs),
+ 	.main_clk	= "uart3_fck",
+ 	.prcm		= {
+ 		.omap2 = {
+ 			.module_offs = CORE_MOD,
+ 			.prcm_reg_id = 2,
+ 			.module_bit = OMAP24XX_EN_UART3_SHIFT,
+ 			.idlest_reg_id = 2,
+ 			.idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
+ 		},
+ 	},
+ 	.slaves		= omap2430_uart3_slaves,
+ 	.slaves_cnt	= ARRAY_SIZE(omap2430_uart3_slaves),
+ 	.class		= &uart_class,
+ 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ };
+ 
  static __initdata struct omap_hwmod *omap2430_hwmods[] = {
  	&omap2430_l3_main_hwmod,
  	&omap2430_l4_core_hwmod,
  	&omap2430_l4_wkup_hwmod,
  	&omap2430_mpu_hwmod,
  	&omap2430_iva_hwmod,
 +	&omap2430_wd_timer2_hwmod,
+ 	&omap2430_uart1_hwmod,
+ 	&omap2430_uart2_hwmod,
+ 	&omap2430_uart3_hwmod,
  	NULL,
  };
  
diff --cc arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 5bfe9c933144,5c9cb255a052..cb97ecf0a3f6
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@@ -199,69 -278,172 +280,235 @@@ static struct omap_hwmod omap3xxx_iva_h
  	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  };
  
 +/* l4_wkup -> wd_timer2 */
 +static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
 +	{
 +		.pa_start	= 0x48314000,
 +		.pa_end		= 0x4831407f,
 +		.flags		= ADDR_TYPE_RT
 +	},
 +};
 +
 +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
 +	.master		= &omap3xxx_l4_wkup_hwmod,
 +	.slave		= &omap3xxx_wd_timer2_hwmod,
 +	.clk		= "wdt2_ick",
 +	.addr		= omap3xxx_wd_timer2_addrs,
 +	.addr_cnt	= ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
 +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
 +/*
 + * 'wd_timer' class
 + * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 + * overflow condition
 + */
 +
 +static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 +	.rev_offs	= 0x0000,
 +	.sysc_offs	= 0x0010,
 +	.syss_offs	= 0x0014,
 +	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 +			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 +			   SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
 +	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 +	.sysc_fields    = &omap_hwmod_sysc_type1,
 +};
 +
 +static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 +	.name = "wd_timer",
 +	.sysc = &omap3xxx_wd_timer_sysc,
 +};
 +
 +/* wd_timer2 */
 +static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
 +	&omap3xxx_l4_wkup__wd_timer2,
 +};
 +
 +static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 +	.name		= "wd_timer2",
 +	.class		= &omap3xxx_wd_timer_hwmod_class,
 +	.main_clk	= "wdt2_fck",
 +	.prcm		= {
 +		.omap2 = {
 +			.prcm_reg_id = 1,
 +			.module_bit = OMAP3430_EN_WDT2_SHIFT,
 +			.module_offs = WKUP_MOD,
 +			.idlest_reg_id = 1,
 +			.idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 +		},
 +	},
 +	.slaves		= omap3xxx_wd_timer2_slaves,
 +	.slaves_cnt	= ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
 +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 +};
 +
+ /* UART common */
+ 
+ static struct omap_hwmod_class_sysconfig uart_sysc = {
+ 	.rev_offs	= 0x50,
+ 	.sysc_offs	= 0x54,
+ 	.syss_offs	= 0x58,
+ 	.sysc_flags	= (SYSC_HAS_SIDLEMODE |
+ 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ 			   SYSC_HAS_AUTOIDLE),
+ 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ 	.sysc_fields    = &omap_hwmod_sysc_type1,
+ };
+ 
+ static struct omap_hwmod_class uart_class = {
+ 	.name = "uart",
+ 	.sysc = &uart_sysc,
+ };
+ 
+ /* UART1 */
+ 
+ static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
+ 	{ .irq = INT_24XX_UART1_IRQ, },
+ };
+ 
+ static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+ 	{ .name = "tx",	.dma_req = OMAP24XX_DMA_UART1_TX, },
+ 	{ .name = "rx",	.dma_req = OMAP24XX_DMA_UART1_RX, },
+ };
+ 
+ static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
+ 	&omap3_l4_core__uart1,
+ };
+ 
+ static struct omap_hwmod omap3xxx_uart1_hwmod = {
+ 	.name		= "uart1",
+ 	.mpu_irqs	= uart1_mpu_irqs,
+ 	.mpu_irqs_cnt	= ARRAY_SIZE(uart1_mpu_irqs),
+ 	.sdma_reqs	= uart1_sdma_reqs,
+ 	.sdma_reqs_cnt	= ARRAY_SIZE(uart1_sdma_reqs),
+ 	.main_clk	= "uart1_fck",
+ 	.prcm		= {
+ 		.omap2 = {
+ 			.module_offs = CORE_MOD,
+ 			.prcm_reg_id = 1,
+ 			.module_bit = OMAP3430_EN_UART1_SHIFT,
+ 			.idlest_reg_id = 1,
+ 			.idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
+ 		},
+ 	},
+ 	.slaves		= omap3xxx_uart1_slaves,
+ 	.slaves_cnt	= ARRAY_SIZE(omap3xxx_uart1_slaves),
+ 	.class		= &uart_class,
+ 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ };
+ 
+ /* UART2 */
+ 
+ static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
+ 	{ .irq = INT_24XX_UART2_IRQ, },
+ };
+ 
+ static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+ 	{ .name = "tx",	.dma_req = OMAP24XX_DMA_UART2_TX, },
+ 	{ .name = "rx",	.dma_req = OMAP24XX_DMA_UART2_RX, },
+ };
+ 
+ static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
+ 	&omap3_l4_core__uart2,
+ };
+ 
+ static struct omap_hwmod omap3xxx_uart2_hwmod = {
+ 	.name		= "uart2",
+ 	.mpu_irqs	= uart2_mpu_irqs,
+ 	.mpu_irqs_cnt	= ARRAY_SIZE(uart2_mpu_irqs),
+ 	.sdma_reqs	= uart2_sdma_reqs,
+ 	.sdma_reqs_cnt	= ARRAY_SIZE(uart2_sdma_reqs),
+ 	.main_clk	= "uart2_fck",
+ 	.prcm		= {
+ 		.omap2 = {
+ 			.module_offs = CORE_MOD,
+ 			.prcm_reg_id = 1,
+ 			.module_bit = OMAP3430_EN_UART2_SHIFT,
+ 			.idlest_reg_id = 1,
+ 			.idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
+ 		},
+ 	},
+ 	.slaves		= omap3xxx_uart2_slaves,
+ 	.slaves_cnt	= ARRAY_SIZE(omap3xxx_uart2_slaves),
+ 	.class		= &uart_class,
+ 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ };
+ 
+ /* UART3 */
+ 
+ static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
+ 	{ .irq = INT_24XX_UART3_IRQ, },
+ };
+ 
+ static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+ 	{ .name = "tx",	.dma_req = OMAP24XX_DMA_UART3_TX, },
+ 	{ .name = "rx",	.dma_req = OMAP24XX_DMA_UART3_RX, },
+ };
+ 
+ static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
+ 	&omap3_l4_per__uart3,
+ };
+ 
+ static struct omap_hwmod omap3xxx_uart3_hwmod = {
+ 	.name		= "uart3",
+ 	.mpu_irqs	= uart3_mpu_irqs,
+ 	.mpu_irqs_cnt	= ARRAY_SIZE(uart3_mpu_irqs),
+ 	.sdma_reqs	= uart3_sdma_reqs,
+ 	.sdma_reqs_cnt	= ARRAY_SIZE(uart3_sdma_reqs),
+ 	.main_clk	= "uart3_fck",
+ 	.prcm		= {
+ 		.omap2 = {
+ 			.module_offs = OMAP3430_PER_MOD,
+ 			.prcm_reg_id = 1,
+ 			.module_bit = OMAP3430_EN_UART3_SHIFT,
+ 			.idlest_reg_id = 1,
+ 			.idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
+ 		},
+ 	},
+ 	.slaves		= omap3xxx_uart3_slaves,
+ 	.slaves_cnt	= ARRAY_SIZE(omap3xxx_uart3_slaves),
+ 	.class		= &uart_class,
+ 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ };
+ 
+ /* UART4 */
+ 
+ static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
+ 	{ .irq = INT_36XX_UART4_IRQ, },
+ };
+ 
+ static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
+ 	{ .name = "rx",	.dma_req = OMAP36XX_DMA_UART4_RX, },
+ 	{ .name = "tx",	.dma_req = OMAP36XX_DMA_UART4_TX, },
+ };
+ 
+ static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
+ 	&omap3_l4_per__uart4,
+ };
+ 
+ static struct omap_hwmod omap3xxx_uart4_hwmod = {
+ 	.name		= "uart4",
+ 	.mpu_irqs	= uart4_mpu_irqs,
+ 	.mpu_irqs_cnt	= ARRAY_SIZE(uart4_mpu_irqs),
+ 	.sdma_reqs	= uart4_sdma_reqs,
+ 	.sdma_reqs_cnt	= ARRAY_SIZE(uart4_sdma_reqs),
+ 	.main_clk	= "uart4_fck",
+ 	.prcm		= {
+ 		.omap2 = {
+ 			.module_offs = OMAP3430_PER_MOD,
+ 			.prcm_reg_id = 1,
+ 			.module_bit = OMAP3630_EN_UART4_SHIFT,
+ 			.idlest_reg_id = 1,
+ 			.idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
+ 		},
+ 	},
+ 	.slaves		= omap3xxx_uart4_slaves,
+ 	.slaves_cnt	= ARRAY_SIZE(omap3xxx_uart4_slaves),
+ 	.class		= &uart_class,
+ 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+ };
+ 
  static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
  	&omap3xxx_l3_main_hwmod,
  	&omap3xxx_l4_core_hwmod,
@@@ -269,7 -451,10 +516,11 @@@
  	&omap3xxx_l4_wkup_hwmod,
  	&omap3xxx_mpu_hwmod,
  	&omap3xxx_iva_hwmod,
 +	&omap3xxx_wd_timer2_hwmod,
+ 	&omap3xxx_uart1_hwmod,
+ 	&omap3xxx_uart2_hwmod,
+ 	&omap3xxx_uart3_hwmod,
+ 	&omap3xxx_uart4_hwmod,
  	NULL,
  };
  
diff --cc arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 9523b4c9537f,afcbd483a6c4..7274db4de487
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@@ -452,136 -452,235 +452,365 @@@ static struct omap_hwmod omap44xx_mpu_h
  	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  };
  
 +/*
 + * 'wd_timer' class
 + * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 + * overflow condition
 + */
 +
 +static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
 +	.rev_offs	= 0x0000,
 +	.sysc_offs	= 0x0010,
 +	.syss_offs	= 0x0014,
 +	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 +			   SYSC_HAS_SOFTRESET),
 +	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 +	.sysc_fields	= &omap_hwmod_sysc_type1,
 +};
 +
+ /*
+  * 'uart' class
+  * universal asynchronous receiver/transmitter (uart)
+  */
+ 
+ static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
+ 	.rev_offs	= 0x0050,
+ 	.sysc_offs	= 0x0054,
+ 	.syss_offs	= 0x0058,
+ 	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ 			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ 	.sysc_fields	= &omap_hwmod_sysc_type1,
+ };
+ 
 +static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
 +	.name = "wd_timer",
 +	.sysc = &omap44xx_wd_timer_sysc,
 +};
 +
 +/* wd_timer2 */
 +static struct omap_hwmod omap44xx_wd_timer2_hwmod;
 +static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
 +	{ .irq = 80 + OMAP44XX_IRQ_GIC_START },
 +};
 +
 +static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
 +	{
 +		.pa_start	= 0x4a314000,
 +		.pa_end		= 0x4a31407f,
 +		.flags		= ADDR_TYPE_RT
 +	},
 +};
 +
+ static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
+ 	.name = "uart",
+ 	.sysc = &omap44xx_uart_sysc,
+ };
+ 
+ /* uart1 */
+ static struct omap_hwmod omap44xx_uart1_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
+ 	{ .irq = 72 + OMAP44XX_IRQ_GIC_START },
+ };
+ 
+ static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
+ 	{ .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
+ 	{ .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
+ };
+ 
+ static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
+ 	{
+ 		.pa_start	= 0x4806a000,
+ 		.pa_end		= 0x4806a0ff,
+ 		.flags		= ADDR_TYPE_RT
+ 	},
+ };
+ 
+ /* l4_per -> uart1 */
+ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
+ 	.master		= &omap44xx_l4_per_hwmod,
+ 	.slave		= &omap44xx_uart1_hwmod,
+ 	.clk		= "l4_div_ck",
+ 	.addr		= omap44xx_uart1_addrs,
+ 	.addr_cnt	= ARRAY_SIZE(omap44xx_uart1_addrs),
+ 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+ };
+ 
+ /* uart1 slave ports */
+ static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
+ 	&omap44xx_l4_per__uart1,
+ };
+ 
+ static struct omap_hwmod omap44xx_uart1_hwmod = {
+ 	.name		= "uart1",
+ 	.class		= &omap44xx_uart_hwmod_class,
+ 	.mpu_irqs	= omap44xx_uart1_irqs,
+ 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_uart1_irqs),
+ 	.sdma_reqs	= omap44xx_uart1_sdma_reqs,
+ 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
+ 	.main_clk	= "uart1_fck",
+ 	.prcm = {
+ 		.omap4 = {
+ 			.clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
+ 		},
+ 	},
+ 	.slaves		= omap44xx_uart1_slaves,
+ 	.slaves_cnt	= ARRAY_SIZE(omap44xx_uart1_slaves),
+ 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+ 
+ /* uart2 */
+ static struct omap_hwmod omap44xx_uart2_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
+ 	{ .irq = 73 + OMAP44XX_IRQ_GIC_START },
+ };
+ 
+ static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
+ 	{ .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
+ 	{ .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
+ };
+ 
+ static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
+ 	{
+ 		.pa_start	= 0x4806c000,
+ 		.pa_end		= 0x4806c0ff,
+ 		.flags		= ADDR_TYPE_RT
+ 	},
+ };
+ 
 +/* l4_wkup -> wd_timer2 */
 +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
 +	.master		= &omap44xx_l4_wkup_hwmod,
 +	.slave		= &omap44xx_wd_timer2_hwmod,
 +	.clk		= "l4_wkup_clk_mux_ck",
 +	.addr		= omap44xx_wd_timer2_addrs,
 +	.addr_cnt	= ARRAY_SIZE(omap44xx_wd_timer2_addrs),
 +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
 +/* wd_timer2 slave ports */
 +static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
 +	&omap44xx_l4_wkup__wd_timer2,
 +};
 +
 +static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
 +	.name		= "wd_timer2",
 +	.class		= &omap44xx_wd_timer_hwmod_class,
 +	.mpu_irqs	= omap44xx_wd_timer2_irqs,
 +	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_wd_timer2_irqs),
 +	.main_clk	= "wd_timer2_fck",
 +	.prcm = {
 +		.omap4 = {
 +			.clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
 +		},
 +	},
 +	.slaves		= omap44xx_wd_timer2_slaves,
 +	.slaves_cnt	= ARRAY_SIZE(omap44xx_wd_timer2_slaves),
 +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 +};
 +
 +/* wd_timer3 */
 +static struct omap_hwmod omap44xx_wd_timer3_hwmod;
 +static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
 +	{ .irq = 36 + OMAP44XX_IRQ_GIC_START },
 +};
 +
 +static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
 +	{
 +		.pa_start	= 0x40130000,
 +		.pa_end		= 0x4013007f,
 +		.flags		= ADDR_TYPE_RT
 +	},
 +};
 +
+ /* l4_per -> uart2 */
+ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
+ 	.master		= &omap44xx_l4_per_hwmod,
+ 	.slave		= &omap44xx_uart2_hwmod,
+ 	.clk		= "l4_div_ck",
+ 	.addr		= omap44xx_uart2_addrs,
+ 	.addr_cnt	= ARRAY_SIZE(omap44xx_uart2_addrs),
+ 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+ };
+ 
+ /* uart2 slave ports */
+ static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
+ 	&omap44xx_l4_per__uart2,
+ };
+ 
+ static struct omap_hwmod omap44xx_uart2_hwmod = {
+ 	.name		= "uart2",
+ 	.class		= &omap44xx_uart_hwmod_class,
+ 	.mpu_irqs	= omap44xx_uart2_irqs,
+ 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_uart2_irqs),
+ 	.sdma_reqs	= omap44xx_uart2_sdma_reqs,
+ 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
+ 	.main_clk	= "uart2_fck",
+ 	.prcm = {
+ 		.omap4 = {
+ 			.clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
+ 		},
+ 	},
+ 	.slaves		= omap44xx_uart2_slaves,
+ 	.slaves_cnt	= ARRAY_SIZE(omap44xx_uart2_slaves),
+ 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+ 
+ /* uart3 */
+ static struct omap_hwmod omap44xx_uart3_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
+ 	{ .irq = 74 + OMAP44XX_IRQ_GIC_START },
+ };
+ 
+ static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
+ 	{ .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
+ 	{ .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
+ };
+ 
+ static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
+ 	{
+ 		.pa_start	= 0x48020000,
+ 		.pa_end		= 0x480200ff,
+ 		.flags		= ADDR_TYPE_RT
+ 	},
+ };
+ 
 +/* l4_abe -> wd_timer3 */
 +static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
 +	.master		= &omap44xx_l4_abe_hwmod,
 +	.slave		= &omap44xx_wd_timer3_hwmod,
 +	.clk		= "ocp_abe_iclk",
 +	.addr		= omap44xx_wd_timer3_addrs,
 +	.addr_cnt	= ARRAY_SIZE(omap44xx_wd_timer3_addrs),
 +	.user		= OCP_USER_MPU,
 +};
 +
 +/* l4_abe -> wd_timer3 (dma) */
 +static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
 +	{
 +		.pa_start	= 0x49030000,
 +		.pa_end		= 0x4903007f,
 +		.flags		= ADDR_TYPE_RT
 +	},
 +};
 +
+ /* l4_per -> uart3 */
+ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
+ 	.master		= &omap44xx_l4_per_hwmod,
+ 	.slave		= &omap44xx_uart3_hwmod,
+ 	.clk		= "l4_div_ck",
+ 	.addr		= omap44xx_uart3_addrs,
+ 	.addr_cnt	= ARRAY_SIZE(omap44xx_uart3_addrs),
+ 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+ };
+ 
+ /* uart3 slave ports */
+ static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
+ 	&omap44xx_l4_per__uart3,
+ };
+ 
+ static struct omap_hwmod omap44xx_uart3_hwmod = {
+ 	.name		= "uart3",
+ 	.class		= &omap44xx_uart_hwmod_class,
+ 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ 	.mpu_irqs	= omap44xx_uart3_irqs,
+ 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_uart3_irqs),
+ 	.sdma_reqs	= omap44xx_uart3_sdma_reqs,
+ 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
+ 	.main_clk	= "uart3_fck",
+ 	.prcm = {
+ 		.omap4 = {
+ 			.clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
+ 		},
+ 	},
+ 	.slaves		= omap44xx_uart3_slaves,
+ 	.slaves_cnt	= ARRAY_SIZE(omap44xx_uart3_slaves),
+ 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+ 
+ /* uart4 */
+ static struct omap_hwmod omap44xx_uart4_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
+ 	{ .irq = 70 + OMAP44XX_IRQ_GIC_START },
+ };
+ 
+ static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
+ 	{ .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
+ 	{ .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
+ };
+ 
+ static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
+ 	{
+ 		.pa_start	= 0x4806e000,
+ 		.pa_end		= 0x4806e0ff,
+ 		.flags		= ADDR_TYPE_RT
+ 	},
+ };
+ 
 +static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
 +	.master		= &omap44xx_l4_abe_hwmod,
 +	.slave		= &omap44xx_wd_timer3_hwmod,
 +	.clk		= "ocp_abe_iclk",
 +	.addr		= omap44xx_wd_timer3_dma_addrs,
 +	.addr_cnt	= ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
 +	.user		= OCP_USER_SDMA,
 +};
 +
 +/* wd_timer3 slave ports */
 +static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
 +	&omap44xx_l4_abe__wd_timer3,
 +	&omap44xx_l4_abe__wd_timer3_dma,
 +};
 +
 +static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
 +	.name		= "wd_timer3",
 +	.class		= &omap44xx_wd_timer_hwmod_class,
 +	.mpu_irqs	= omap44xx_wd_timer3_irqs,
 +	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_wd_timer3_irqs),
 +	.main_clk	= "wd_timer3_fck",
 +	.prcm = {
 +		.omap4 = {
 +			.clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
 +		},
 +	},
 +	.slaves		= omap44xx_wd_timer3_slaves,
 +	.slaves_cnt	= ARRAY_SIZE(omap44xx_wd_timer3_slaves),
 +	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 +};
 +
+ /* l4_per -> uart4 */
+ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
+ 	.master		= &omap44xx_l4_per_hwmod,
+ 	.slave		= &omap44xx_uart4_hwmod,
+ 	.clk		= "l4_div_ck",
+ 	.addr		= omap44xx_uart4_addrs,
+ 	.addr_cnt	= ARRAY_SIZE(omap44xx_uart4_addrs),
+ 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+ };
+ 
+ /* uart4 slave ports */
+ static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
+ 	&omap44xx_l4_per__uart4,
+ };
+ 
+ static struct omap_hwmod omap44xx_uart4_hwmod = {
+ 	.name		= "uart4",
+ 	.class		= &omap44xx_uart_hwmod_class,
+ 	.mpu_irqs	= omap44xx_uart4_irqs,
+ 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_uart4_irqs),
+ 	.sdma_reqs	= omap44xx_uart4_sdma_reqs,
+ 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
+ 	.main_clk	= "uart4_fck",
+ 	.prcm = {
+ 		.omap4 = {
+ 			.clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
+ 		},
+ 	},
+ 	.slaves		= omap44xx_uart4_slaves,
+ 	.slaves_cnt	= ARRAY_SIZE(omap44xx_uart4_slaves),
+ 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+ 
  static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
  	/* dmm class */
  	&omap44xx_dmm_hwmod,
@@@ -602,9 -701,12 +831,15 @@@
  
  	/* mpu class */
  	&omap44xx_mpu_hwmod,
 +	/* wd_timer class */
 +	&omap44xx_wd_timer2_hwmod,
 +	&omap44xx_wd_timer3_hwmod,
+ 
+ 	/* uart class */
+ 	&omap44xx_uart1_hwmod,
+ 	&omap44xx_uart2_hwmod,
+ 	&omap44xx_uart3_hwmod,
+ 	&omap44xx_uart4_hwmod,
  	NULL,
  };