From: Rajendra Nayak <rnayak@ti.com>
Date: Wed, 4 Apr 2012 16:20:01 +0000 (-0600)
Subject: ARM: OMAP4: clock data: Force a DPLL clkdm/pwrdm ON before a relock
X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=6c4a057bffe9823221eab547e11fac181dc18a2b;p=linux-beck.git

ARM: OMAP4: clock data: Force a DPLL clkdm/pwrdm ON before a relock

All DPLLs except USB are in ALWON powerdomain. Make sure the
clkdm/pwrdm for USB DPLL (l3init) is turned on before attempting
a DPLL relock. So, mark the database accordingly.

Without this fix, it was seen that DPLL relock fails while testing
relock in a loop of USB DPLL.

Cc: Nishanth Menon <nm@ti.com>
Tested-by: Ameya Palande <ameya.palande@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---

diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 984904fcd244..fa6ea65ad44b 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -978,6 +978,7 @@ static struct clk dpll_usb_ck = {
 	.recalc		= &omap3_dpll_recalc,
 	.round_rate	= &omap2_dpll_round_rate,
 	.set_rate	= &omap3_noncore_dpll_set_rate,
+	.clkdm_name	= "l3_init_clkdm",
 };
 
 static struct clk dpll_usb_clkdcoldo_ck = {