From: Paulo Zanoni Date: Wed, 31 Oct 2012 20:12:39 +0000 (-0200) Subject: drm/i915: don't call ironlake_enable_pch_pll on lpt_pch_enable X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=7cbfd0653005d6c7a8f00d8ef5573b2976157780;p=linux-beck.git drm/i915: don't call ironlake_enable_pch_pll on lpt_pch_enable This is just wrong. The lpt_program_iclkip should disable the PCH pixel clocks (and yes, we plan to rename it later). Signed-off-by: Paulo Zanoni Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 22da6d1279d7..88dd4c1a4c88 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3181,15 +3181,6 @@ static void lpt_pch_enable(struct drm_crtc *crtc) /* For PCH output, training FDI link */ dev_priv->display.fdi_link_train(crtc); - /* XXX: pch pll's can be enabled any time before we enable the PCH - * transcoder, and we actually should do this to not upset any PCH - * transcoder that already use the clock when we share it. - * - * Note that enable_pch_pll tries to do the right thing, but get_pch_pll - * unconditionally resets the pll - we need that to have the right LVDS - * enable sequence. */ - ironlake_enable_pch_pll(intel_crtc); - lpt_program_iclkip(crtc); /* set transcoder timing, panel must allow it */