From: Anson Huang <b20788@freescale.com>
Date: Tue, 10 Sep 2013 20:22:20 +0000 (-0400)
Subject: ENGR00278941-1: arm: imx: Fix suspend/resume unstable issue
X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=857b8bd8cdd22407f9378761be41ad93225c2747;p=karo-tx-linux.git

ENGR00278941-1: arm: imx: Fix suspend/resume unstable issue

As we need to float DDR IO when entering DSM, so those registers
we need to access after DDR IO is floated must be contained in TLB,
otherwise, the TLB update may case DDR access and lead to
system hang. To make sure these registers' address is in TLB,
we need to flush TLB first then access them manually.

Signed-off-by: Anson Huang <b20788@freescale.com>
---

diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index dc638a533948..1efe20c5f27d 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -25,6 +25,7 @@
 #include <asm/fncpy.h>
 #include <asm/proc-fns.h>
 #include <asm/suspend.h>
+#include <asm/tlb.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
 
@@ -212,6 +213,7 @@ static int imx6_suspend_finish(unsigned long val)
 	 * call low level suspend function in iram,
 	 * as we need to float DDR IO.
 	 */
+	local_flush_tlb_all();
 	suspend_in_iram_fn(suspend_iram_base, iram_paddr, cpu_type);
 	return 0;
 }