From: Koji Matsuoka Date: Tue, 28 Jun 2016 07:33:45 +0000 (+0900) Subject: drm: rcar-du: Fix LVDS start sequence on Gen3 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=85e8f8d175caa6a39f4c4e11dd4d0ab038f43324;p=linux-beck.git drm: rcar-du: Fix LVDS start sequence on Gen3 According to the latest revision of the datasheet, the LVDS I/O pins must be enabled before starting the PLL. Fix it. Signed-off-by: Koji Matsuoka Signed-off-by: Laurent Pinchart --- diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c index b74105a80a6e..e3a4985f6f3f 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c @@ -104,7 +104,14 @@ static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds, rcar_lvds_write(lvds, LVDPLLCR, pllcr); - /* Turn the PLL on, set it to LVDS normal mode, wait for the startup + /* Turn all the channels on. */ + rcar_lvds_write(lvds, LVDCR1, + LVDCR1_CHSTBY_GEN3(3) | LVDCR1_CHSTBY_GEN3(2) | + LVDCR1_CHSTBY_GEN3(1) | LVDCR1_CHSTBY_GEN3(0) | + LVDCR1_CLKSTBY_GEN3); + + /* + * Turn the PLL on, set it to LVDS normal mode, wait for the startup * delay and turn the output on. */ lvdcr0 = LVDCR0_PLLON; @@ -117,12 +124,6 @@ static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds, lvdcr0 |= LVDCR0_LVRES; rcar_lvds_write(lvds, LVDCR0, lvdcr0); - - /* Turn all the channels on. */ - rcar_lvds_write(lvds, LVDCR1, - LVDCR1_CHSTBY_GEN3(3) | LVDCR1_CHSTBY_GEN3(2) | - LVDCR1_CHSTBY_GEN3(1) | LVDCR1_CHSTBY_GEN3(0) | - LVDCR1_CLKSTBY_GEN3); } static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,