From: Andrew Chew Date: Wed, 7 Aug 2013 11:25:09 +0000 (+0800) Subject: clk: tegra: Set the clk parent of host1x to pll_p X-Git-Tag: next-20131210~6^2~1^2~35 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=897e1dde1ec1571a28545594633624927fa0a76e;p=karo-tx-linux.git clk: tegra: Set the clk parent of host1x to pll_p The power-on default parent for this clock is pll_m, which turns out to be wrong. Previously, bootloader reparented this clock. We'll do it in the kernel as well, so that there's one less thing that we depend on bootloader to initialize. Signed-off-by: Andrew Chew Signed-off-by: Mark Zhang --- diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index e3904923005b..9b8c938477de 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -2183,6 +2183,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { {TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, {TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, {TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, + {TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0}, {TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1}, {TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1}, {TEGRA114_CLK_GR_2D, TEGRA114_CLK_PLL_C2, 300000000, 0},