From: Heiko Stuebner Date: Tue, 1 Dec 2015 21:23:45 +0000 (+0100) Subject: clk: rockchip: fix rk3368 cpuclk divider offsets X-Git-Tag: v4.5-rc1~82^2~10^2~5 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=8ad0df33c62d706f925a5910701255759a68c2e5;p=karo-tx-linux.git clk: rockchip: fix rk3368 cpuclk divider offsets Due to a copy-paste error the the rk3368 cpuclk settings were acessing rk3288-specific register offsets. This never caused problems till now, as cpu frequency scaling in't used currently at all. Reported-by: Xing Zheng Signed-off-by: Heiko Stuebner --- diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c index 4d2e7e56ee68..1faf1602a3fc 100644 --- a/drivers/clk/rockchip/clk-rk3368.c +++ b/drivers/clk/rockchip/clk-rk3368.c @@ -184,13 +184,13 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = { #define RK3368_CLKSEL0(_offs, _aclkm) \ { \ - .reg = RK3288_CLKSEL_CON(0 + _offs), \ + .reg = RK3368_CLKSEL_CON(0 + _offs), \ .val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK, \ RK3368_DIV_ACLKM_SHIFT), \ } #define RK3368_CLKSEL1(_offs, _atclk, _pdbg) \ { \ - .reg = RK3288_CLKSEL_CON(1 + _offs), \ + .reg = RK3368_CLKSEL_CON(1 + _offs), \ .val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK, \ RK3368_DIV_ATCLK_SHIFT) | \ HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK, \