From: Dave Airlie Date: Tue, 18 Mar 2014 09:06:53 +0000 (+1000) Subject: Merge branch 'drm-intel-next' of git://git.freedesktop.org/git/drm-intel into drm... X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=8ad2bc9796994ecba9f4ba2fc9abca27ee9d193d;p=linux-beck.git Merge branch 'drm-intel-next' of git://git.freedesktop.org/git/drm-intel into drm-next - fine-grained display power domains for byt (Imre) - runtime pm prep patches for !hsw from Paulo - WiZ hashing flag updates from Ville - ppgtt setup cleanup and enabling of full 4G range on bdw (Ben) - fixes from Jesse for the inherited intial config code - gpu reset code improvements from Mika - per-pipe num_planes refactoring from Damien - stability fixes around bdw forcewake handling and other bdw w/a from Mika Ken - and as usual a pile of smaller fixes all over * 'drm-intel-next' of git://git.freedesktop.org/git/drm-intel: (107 commits) drm/i915: Go OCD on the Makefile drm/i915: Implement command buffer parsing logic drm/i915: Refactor shmem pread setup drm/i915: Avoid div by zero when pixel clock is large drm/i915: power domains: add vlv power wells drm/i915: factor out intel_set_cpu_fifo_underrun_reporting_nolock drm/i915: vlv: factor out valleyview_display_irq_install drm/i915: sanity check power well sw state against hw state drm/i915: factor out reset_vblank_counter drm/i915: sanitize PUNIT register macro definitions drm/i915: vlv: keep first level vblank IRQs masked drm/i915: check pipe power domain when reading its hw state drm/i915: check port power domain when reading the encoder hw state drm/i915: get port power domain in connector detect handlers drm/i915: add port power domains drm/i915: add noop power well handlers instead of NULL checking them drm/i915: split power well 'set' handler to separate enable/disable/sync_hw drm/i915: add init power domain to always-on power wells drm/i915: move power domain macros to intel_pm.c drm/i915: Disable full ppgtt by default ... --- 8ad2bc9796994ecba9f4ba2fc9abca27ee9d193d