From: Geert Uytterhoeven Date: Wed, 30 Sep 2015 13:22:15 +0000 (+0200) Subject: arm64: dts: r8a7795: Add CA53 L2 cache-controller node X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=8e1c3aa30c2c3a5f982da9365a1ef03a3ac7a815;p=linux-beck.git arm64: dts: r8a7795: Add CA53 L2 cache-controller node Add a device node for the Cortex-A53 L2 cache-controller. The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as 32 KiB x 16 ways). Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index ea56066c2260..e32b652c8fd0 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -72,6 +72,12 @@ cache-level = <2>; }; + L2_CA53: cache-controller@1 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>;