From: Sebastian Hesselbarth Date: Sun, 11 May 2014 19:32:41 +0000 (+0200) Subject: ARM: dts: berlin: convert BG2 to DT clock nodes X-Git-Tag: next-20140516~110^2~1^2~3 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=8fefbaf0446ac9604308a9c5f5d05d1a8cb613ea;p=karo-tx-linux.git ARM: dts: berlin: convert BG2 to DT clock nodes This converts Berlin BG2 SoC dtsi to make use of the new DT clock nodes for Berlin SoCs. While at it, also fix up twdclk which is running at cpuclk/3 instead of sysclk. Signed-off-by: Sebastian Hesselbarth --- diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index 57cadd31f4e1..edeecb711e97 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -12,6 +12,7 @@ */ #include "skeleton.dtsi" +#include #include / { @@ -37,24 +38,18 @@ }; }; - clocks { - smclk: sysmgr-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - cfgclk: cfg-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; - sysclk: system-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <400000000>; - }; + twdclk: twdclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&coreclk CLKID_CPU>; + clock-mult = <1>; + clock-div = <3>; }; soc { @@ -88,7 +83,7 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0xad0600 0x20>; interrupts = ; - clocks = <&sysclk>; + clocks = <&twdclk>; }; apb@e80000 { @@ -175,7 +170,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c00 0x14>; interrupts = <8>; - clocks = <&cfgclk>; + clocks = <&coreclk CLKID_CFG>; clock-names = "timer"; status = "okay"; }; @@ -184,7 +179,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c14 0x14>; interrupts = <9>; - clocks = <&cfgclk>; + clocks = <&coreclk CLKID_CFG>; clock-names = "timer"; status = "okay"; }; @@ -193,7 +188,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c28 0x14>; interrupts = <10>; - clocks = <&cfgclk>; + clocks = <&coreclk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -202,7 +197,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c3c 0x14>; interrupts = <11>; - clocks = <&cfgclk>; + clocks = <&coreclk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -211,7 +206,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c50 0x14>; interrupts = <12>; - clocks = <&cfgclk>; + clocks = <&coreclk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -220,7 +215,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c64 0x14>; interrupts = <13>; - clocks = <&cfgclk>; + clocks = <&coreclk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -229,7 +224,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c78 0x14>; interrupts = <14>; - clocks = <&cfgclk>; + clocks = <&coreclk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -238,7 +233,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c8c 0x14>; interrupts = <15>; - clocks = <&cfgclk>; + clocks = <&coreclk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -253,11 +248,165 @@ }; }; + syspll: syspll@ea0014 { + compatible = "marvell,berlin2-pll"; + #clock-cells = <0>; + reg = <0xea0014 0x14>; + clocks = <&refclk>; + }; + + mempll: mempll@ea0028 { + compatible = "marvell,berlin2-pll"; + #clock-cells = <0>; + reg = <0xea0028 0x14>; + clocks = <&refclk>; + }; + + cpupll: cpupll@ea003c { + compatible = "marvell,berlin2-pll"; + #clock-cells = <0>; + reg = <0xea003c 0x14>; + clocks = <&refclk>; + }; + + avpll: avpll@ea0040 { + compatible = "marvell,berlin2-avpll"; + #clock-cells = <2>; + reg = <0xea0050 0x100>; + clocks = <&refclk>; + }; + + coreclk: core-clock@ea0150 { + compatible = "marvell,berlin2-core-clocks"; + #clock-cells = <1>; + reg = <0xea0150 0x1c>; + clocks = <&refclk>, <&syspll>, <&mempll>, <&cpupll>, + <&avpll 0 1>, <&avpll 0 2>, + <&avpll 0 3>, <&avpll 0 4>, + <&avpll 0 5>, <&avpll 0 6>, + <&avpll 0 7>, <&avpll 0 8>, + <&avpll 1 1>, <&avpll 1 2>, + <&avpll 1 3>, <&avpll 1 4>, + <&avpll 1 5>, <&avpll 1 6>, + <&avpll 1 7>, <&avpll 1 8>; + clock-names = "refclk", "syspll", "mempll", "cpupll", + "avpll_a1", "avpll_a2", "avpll_a3", "avpll_a4", + "avpll_a5", "avpll_a6", "avpll_a7", "avpll_a8", + "avpll_b1", "avpll_b2", "avpll_b3", "avpll_b4", + "avpll_b5", "avpll_b6", "avpll_b7", "avpll_b8"; + clock-output-names = "sys", "cpu", "drmfigo", "cfg", + "gfx", "zsp", "perif", "pcube", "vscope", + "nfc_ecc", "vpp", "app", "audio0", "audio2", + "audio3", "audio1", "geth0", "geth1", "sata", + "ahbapb", "usb0", "usb1", "pbridge", "sdio0", + "sdio1", "nfc", "smemc", "audiohd", "video0", + "video1", "video2"; + }; + generic-regs@ea0184 { compatible = "marvell,berlin-generic-regs", "syscon"; reg = <0xea0184 0x10>; }; + gfx3dcore_clk: gfx3dcore@ea022c { + compatible = "marvell,berlin2-clk-div"; + #clock-cells = <0>; + reg = <0xea022c 0x4>; + clocks = <&syspll>, + <&avpll 1 4>, <&avpll 1 5>, + <&avpll 1 6>, <&avpll 1 7>; + clock-names = "mux_bypass", + "mux0", "mux1", "mux2", "mux3"; + }; + + gfx3dsys_clk: gfx3dsys@ea0230 { + compatible = "marvell,berlin2-clk-div"; + #clock-cells = <0>; + reg = <0xea0230 0x4>; + clocks = <&syspll>, + <&avpll 1 4>, <&avpll 1 5>, + <&avpll 1 6>, <&avpll 1 7>; + clock-names = "mux_bypass", + "mux0", "mux1", "mux2", "mux3"; + }; + + arc_clk: arc@ea0234 { + compatible = "marvell,berlin2-clk-div"; + #clock-cells = <0>; + reg = <0xea0234 0x4>; + clocks = <&syspll>, + <&avpll 1 4>, <&avpll 1 5>, + <&avpll 1 6>, <&avpll 1 7>; + clock-names = "mux_bypass", + "mux0", "mux1", "mux2", "mux3"; + }; + + vip_clk: vip@ea0238 { + compatible = "marvell,berlin2-clk-div"; + #clock-cells = <0>; + reg = <0xea0238 0x4>; + clocks = <&syspll>, + <&avpll 1 4>, <&avpll 1 5>, + <&avpll 1 6>, <&avpll 1 7>; + clock-names = "mux_bypass", + "mux0", "mux1", "mux2", "mux3"; + }; + + sdio0xin_clk: sdio0xin@ea023c { + compatible = "marvell,berlin2-clk-div"; + #clock-cells = <0>; + reg = <0xea023c 0x4>; + clocks = <&syspll>, + <&avpll 1 4>, <&avpll 1 5>, + <&avpll 1 6>, <&avpll 1 7>; + clock-names = "mux_bypass", + "mux0", "mux1", "mux2", "mux3"; + }; + + sdio1xin_clk: sdio1xin@ea0240 { + compatible = "marvell,berlin2-clk-div"; + #clock-cells = <0>; + reg = <0xea0240 0x4>; + clocks = <&syspll>, + <&avpll 1 4>, <&avpll 1 5>, + <&avpll 1 6>, <&avpll 1 7>; + clock-names = "mux_bypass", + "mux0", "mux1", "mux2", "mux3"; + }; + + gfx3dextra_clk: gfx3dextra@ea0244 { + compatible = "marvell,berlin2-clk-div"; + #clock-cells = <0>; + reg = <0xea0244 0x4>; + clocks = <&syspll>, + <&avpll 1 4>, <&avpll 1 5>, + <&avpll 1 6>, <&avpll 1 7>; + clock-names = "mux_bypass", + "mux0", "mux1", "mux2", "mux3"; + }; + + gc360_clk: gc360@ea024c { + compatible = "marvell,berlin2-clk-div"; + #clock-cells = <0>; + reg = <0xea024c 0x4>; + clocks = <&syspll>, + <&avpll 1 4>, <&avpll 1 5>, + <&avpll 1 6>, <&avpll 1 7>; + clock-names = "mux_bypass", + "mux0", "mux1", "mux2", "mux3"; + }; + + sdio_dllmst_clk: sdio_dllmst@ea0250 { + compatible = "marvell,berlin2-clk-div"; + #clock-cells = <0>; + reg = <0xea0250 0x4>; + clocks = <&syspll>, + <&avpll 1 4>, <&avpll 1 5>, + <&avpll 1 6>, <&avpll 1 7>; + clock-names = "mux_bypass", + "mux0", "mux1", "mux2", "mux3"; + }; + apb@fc0000 { compatible = "simple-bus"; #address-cells = <1>; @@ -305,7 +454,7 @@ reg-shift = <2>; reg-io-width = <1>; interrupts = <8>; - clocks = <&smclk>; + clocks = <&refclk>; status = "disabled"; }; @@ -315,7 +464,7 @@ reg-shift = <2>; reg-io-width = <1>; interrupts = <9>; - clocks = <&smclk>; + clocks = <&refclk>; status = "disabled"; }; @@ -325,7 +474,7 @@ reg-shift = <2>; reg-io-width = <1>; interrupts = <10>; - clocks = <&smclk>; + clocks = <&refclk>; status = "disabled"; };