From: Mike Frysinger <vapier.adi@gmail.com>
Date: Wed, 7 Jan 2009 15:14:38 +0000 (+0800)
Subject: Blackfin arch: do not allow L2 to be cached on BF561 SMP
X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=94106e0fb6b863348a566617ca6bf431c37ddc5e;p=linux-beck.git

Blackfin arch: do not allow L2 to be cached on BF561 SMP

Signed-off-by: Bryan Wu <cooloney@kernel.org>
---

diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index b8bc5a402fa4..f8edfbe5faed 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -866,7 +866,7 @@ endchoice
 
 config BFIN_L2_CACHEABLE
 	bool "Cache L2 SRAM"
-	depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
+	depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP))
 	default n
 	help
 	  Select to make L2 SRAM cacheable in L1 data and instruction cache.