From: Borislav Petkov Date: Tue, 21 Oct 2014 20:19:59 +0000 (+0200) Subject: x86, MCE, AMD: Drop software-defined bank in error thresholding X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=a3a529d104ec5149fb9a667dce988635941be1ed;p=linux-beck.git x86, MCE, AMD: Drop software-defined bank in error thresholding Aravind had the good question about why we're assigning a software-defined bank when reporting error thresholding errors instead of simply using the bank which reports the last error causing the overflow. Digging through git history, it pointed to 95268664390b ("[PATCH] x86_64: mce_amd support for family 0x10 processors") which added that functionality. The problem with this, however, is that tools don't know about software-defined banks and get puzzled. So drop that K8_MCE_THRESHOLD_BASE and simply use the hw bank reporting the thresholding interrupt. Save us a couple of MSR reads while at it. Reported-by: Aravind Gopalakrishnan Link: https://lkml.kernel.org/r/5435B206.60402@amd.com Signed-off-by: Borislav Petkov --- diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 958b90f761e5..276392f121fb 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -78,7 +78,6 @@ /* Software defined banks */ #define MCE_EXTENDED_BANK 128 #define MCE_THERMAL_BANK (MCE_EXTENDED_BANK + 0) -#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) #define MCE_LOG_LEN 32 #define MCE_LOG_SIGNATURE "MACHINECHECK" diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index 9af7bd74828b..6606523ff1c1 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -318,10 +318,9 @@ static void amd_threshold_interrupt(void) log: mce_setup(&m); - rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); - rdmsrl(address, m.misc); rdmsrl(MSR_IA32_MCx_STATUS(bank), m.status); - m.bank = K8_MCE_THRESHOLD_BASE + bank * NR_BLOCKS + block; + m.misc = ((u64)high << 32) | low; + m.bank = bank; mce_log(&m); wrmsrl(MSR_IA32_MCx_STATUS(bank), 0);