From: Stany MARCEL Date: Tue, 16 Oct 2012 05:26:11 +0000 (+1000) Subject: m68k: Set ColdFire ACR1 cache mode depending on kernel configuration X-Git-Tag: v3.10-rc1~17^2~7 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=a4eff487da4e4e55a15da2a8e8769151b1881a95;p=karo-tx-linux.git m68k: Set ColdFire ACR1 cache mode depending on kernel configuration For coldfire with MMU enabled, data cache did not follow the configuration but was configured in writethrough mode. Signed-off-by: Stany MARCEL Signed-off-by: Greg Ungerer --- diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index 192bbfeabf70..6d13cae44af5 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h @@ -96,8 +96,13 @@ */ #define ACR0_MODE (ACR_BA(CONFIG_MBAR)+ACR_ADMSK(0x1000000)+ \ ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP) +#if defined(CONFIG_CACHE_COPYBACK) #define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ - ACR_ENABLE+ACR_SUPER+ACR_SP) + ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_CP) +#else +#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ + ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_WT) +#endif #define ACR2_MODE 0 #define ACR3_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ ACR_ENABLE+ACR_SUPER+ACR_SP)