From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 16 Oct 2012 22:23:05 +0000 (+0200)
Subject: Merge branch 'next/p1/for-linus' into mips-for-linux-next
X-Git-Tag: next-20121017~70^2
X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=a52d0060ca530c70fe2f61e7c3956baaa661a122;p=karo-tx-linux.git

Merge branch 'next/p1/for-linus' into mips-for-linux-next
---

a52d0060ca530c70fe2f61e7c3956baaa661a122
diff --cc arch/mips/mm/tlbex.c
index ea2375b2c565,2833dcb67b5a..753385087b2e
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@@ -181,40 -181,34 +181,64 @@@ UASM_L_LA(_large_segbits_fault
  UASM_L_LA(_tlb_huge_update)
  #endif
  
+ static int __cpuinitdata hazard_instance;
+ 
+ static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance)
+ {
+ 	switch (instance) {
+ 	case 0 ... 7:
+ 		uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance);
+ 		return;
+ 	default:
+ 		BUG();
+ 	}
+ }
+ 
+ static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance)
+ {
+ 	switch (instance) {
+ 	case 0 ... 7:
+ 		uasm_build_label(l, *p, label_tlbw_hazard_0 + instance);
+ 		break;
+ 	default:
+ 		BUG();
+ 	}
+ }
+ 
  /*
 - * For debug purposes.
 + * pgtable bits are assigned dynamically depending on processor feature
 + * and statically based on kernel configuration.  This spits out the actual
 + * values the kernel is using.  Required to make sense from disassembled
 + * TLB exception handlers.
   */
 -static inline void dump_handler(const u32 *handler, int count)
 +static void output_pgtable_bits_defines(void)
 +{
 +#define pr_define(fmt, ...)					\
 +	pr_debug("#define " fmt, ##__VA_ARGS__)
 +
 +	pr_debug("#include <asm/asm.h>\n");
 +	pr_debug("#include <asm/regdef.h>\n");
 +	pr_debug("\n");
 +
 +	pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
 +	pr_define("_PAGE_READ_SHIFT %d\n", _PAGE_READ_SHIFT);
 +	pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
 +	pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT);
 +	pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT);
 +	pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
 +	pr_define("_PAGE_SPLITTING_SHIFT %d\n", _PAGE_SPLITTING_SHIFT);
 +	if (cpu_has_rixi) {
 +		pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
 +		pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
 +	}
 +	pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
 +	pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
 +	pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
 +	pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
 +	pr_debug("\n");
 +}
 +
 +static inline void dump_handler(const char *symbol, const u32 *handler, int count)
  {
  	int i;
  
@@@ -525,6 -516,14 +549,13 @@@ static void __cpuinit build_tlb_write_e
  		uasm_i_nop(p);
  		break;
  
+ 	case CPU_R5000:
 -	case CPU_R5000A:
+ 	case CPU_NEVADA:
+ 		uasm_i_nop(p); /* QED specifies 2 nops hazard */
+ 		uasm_i_nop(p); /* QED specifies 2 nops hazard */
+ 		tlbw(p);
+ 		break;
+ 
  	case CPU_R4300:
  	case CPU_5KC:
  	case CPU_TX49XX: