From: Thierry Reding Date: Tue, 8 Sep 2015 09:38:03 +0000 (+0200) Subject: ARM: tegra124: Clear IDDQ when enabling PLLC X-Git-Tag: KARO-TXSD-2017-03-15~3246 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=aba11d4476b56eb7712184597eb303ae544f0c69;p=karo-tx-uboot.git ARM: tegra124: Clear IDDQ when enabling PLLC Enabling a PLL while IDDQ is high. The Linux kernel checks for this condition and warns about it verbosely, so while this seems to work fine, fix it up according to the programming guidelines provided in the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup Sequence"). Reported-by: Nicolas Chauvet Signed-off-by: Thierry Reding Signed-off-by: Tom Warren --- diff --git a/arch/arm/include/asm/arch-tegra124/clock.h b/arch/arm/include/asm/arch-tegra124/clock.h index e202cc5a7f..ff99b9dfaf 100644 --- a/arch/arm/include/asm/arch-tegra124/clock.h +++ b/arch/arm/include/asm/arch-tegra124/clock.h @@ -16,6 +16,9 @@ #define OSC_FREQ_SHIFT 28 #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) +/* CLK_RST_CONTROLLER_PLLC_MISC_0 */ +#define PLLC_IDDQ (1 << 26) + /* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */ #define SOR0_CLK_SEL0 (1 << 14) #define SOR0_CLK_SEL1 (1 << 15) diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index aa046e8950..1e71146236 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -809,6 +809,11 @@ void clock_early_init(void) tegra30_set_up_pllp(); + /* clear IDDQ before accessing any other PLLC registers */ + pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; + clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); + udelay(2); + /* * PLLC output frequency set to 600Mhz * PLLD output frequency set to 925Mhz