From: Vivek Gautam Date: Wed, 18 Jan 2017 06:32:52 +0000 (+0530) Subject: arm64: dts: exynos: Add USB 3.0 controller node for Exynos7 X-Git-Tag: v4.11-rc1~12^2~3^2~1^2~1 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=ad6afec832a77845a9a0f9353fe049225a976b16;p=karo-tx-linux.git arm64: dts: exynos: Add USB 3.0 controller node for Exynos7 Add USB 3.0 DRD controller device node, with its clock and phy information to enable the same on Exynos7. Signed-off-by: Vivek Gautam Signed-off-by: Pankaj Dubey Reviewed-by: Javier Martinez Canillas Reviewed-by: Alim Akhtar Signed-off-by: Krzysztof Kozlowski --- diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 80aa60e38237..9a3fbed1765a 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -603,6 +603,40 @@ #include "exynos7-trip-points.dtsi" }; }; + + usbdrd_phy: phy@15500000 { + compatible = "samsung,exynos7-usbdrd-phy"; + reg = <0x15500000 0x100>; + clocks = <&clock_fsys0 ACLK_USBDRD300>, + <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>, + <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, + <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>, + <&clock_fsys0 SCLK_USBDRD300_REFCLK>; + clock-names = "phy", "ref", "phy_pipe", + "phy_utmi", "itp"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + }; + + usbdrd3 { + compatible = "samsung,exynos7-dwusb3"; + clocks = <&clock_fsys0 ACLK_USBDRD300>, + <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>, + <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>; + clock-names = "usbdrd30", "usbdrd30_susp_clk", + "usbdrd30_axius_clk"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dwc3@15400000 { + compatible = "snps,dwc3"; + reg = <0x15400000 0x10000>; + interrupts = ; + phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; }; };