From: Andrew Bresticker Date: Thu, 18 Jun 2015 21:28:37 +0000 (-0400) Subject: clk: tegra: pll: Fix issues with rates for VCO PLLs X-Git-Tag: v4.5-rc1~82^2~1^2~2 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=afff455cf4f2501d30446eefbfd0aecb14b8a0b8;p=karo-tx-linux.git clk: tegra: pll: Fix issues with rates for VCO PLLs Without this change clk_get_rate would return the final output rather than the VCO output as it would factor in the pdiv when it shouldn't. This will cause problems for all dividers in the subtree of the VCO PLL. Signed-off-by: Andrew Bresticker Reviewed-by: Benson Leung Signed-off-by: Rhyland Klein Signed-off-by: Thierry Reding --- diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index d00e3289eb79..731c6857c895 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -752,6 +752,8 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, spin_lock_irqsave(pll->lock, flags); _get_pll_mnp(pll, &old_cfg); + if (pll->params->flags & TEGRA_PLL_VCO_OUT) + cfg.p = old_cfg.p; if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p || old_cfg.sdm_data != cfg.sdm_data) @@ -812,11 +814,15 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, _get_pll_mnp(pll, &cfg); - pdiv = _hw_to_p_div(hw, cfg.p); - if (pdiv < 0) { - WARN(1, "Clock %s has invalid pdiv value : 0x%x\n", - __clk_get_name(hw->clk), cfg.p); + if (pll->params->flags & TEGRA_PLL_VCO_OUT) { pdiv = 1; + } else { + pdiv = _hw_to_p_div(hw, cfg.p); + if (pdiv < 0) { + WARN(1, "Clock %s has invalid pdiv value : 0x%x\n", + clk_hw_get_name(hw), cfg.p); + pdiv = 1; + } } if (pll->params->set_gain) @@ -1103,6 +1109,8 @@ static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate, spin_lock_irqsave(pll->lock, flags); _get_pll_mnp(pll, &old_cfg); + if (pll->params->flags & TEGRA_PLL_VCO_OUT) + cfg.p = old_cfg.p; if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p) ret = _program_pll(hw, &cfg, rate);