From: Priit Laes Date: Thu, 2 Mar 2017 20:55:27 +0000 (+0200) Subject: clk: sunxi-ng: sun5i: Fix mux width for csi clock X-Git-Tag: v4.12-rc1~30^2~40^2~6 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=b0f0daa8fe9e74b85f6360288d38224ad1c2f2f4;p=karo-tx-linux.git clk: sunxi-ng: sun5i: Fix mux width for csi clock Mux for CSI clock is 3 bits, not 2. Signed-off-by: Priit Laes Signed-off-by: Maxime Ripard --- diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.c b/drivers/clk/sunxi-ng/ccu-sun5i.c index 06edaa523479..5c476f966a72 100644 --- a/drivers/clk/sunxi-ng/ccu-sun5i.c +++ b/drivers/clk/sunxi-ng/ccu-sun5i.c @@ -469,7 +469,7 @@ static const char * const csi_parents[] = { "hosc", "pll-video0", "pll-video1", static const u8 csi_table[] = { 0, 1, 2, 5, 6 }; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi", csi_parents, csi_table, - 0x134, 0, 5, 24, 2, BIT(31), 0); + 0x134, 0, 5, 24, 3, BIT(31), 0); static SUNXI_CCU_GATE(ve_clk, "ve", "pll-ve", 0x13c, BIT(31), CLK_SET_RATE_PARENT);